| Issue |
145618
|
| Summary |
[RISCV] Hints and Custom Extensions (specifically Xqci)
|
| Labels |
backend:RISC-V
|
| Assignees |
|
| Reporter |
lenary
|
The description of the C/Zca hints has recently been updated https://github.com/riscv/riscv-isa-manual/pull/2093 . This has made some clarifications and minor updates to how hints are defined.
This issue is to look at how this affects Xqci, which uses some of the custom hint space for some of its instructions. I've noted the ones in the custom space, and those in the HINT space. I've also noted where the operation of an instruction is "hint-compatible" - i.e. it has microarchitectural implications but no register state is updated.
Xqci is rv32-only.
Relevant Instructions:
- `C.SRLI` with `shamt[5] == 1` (custom on rv32)
- `QC.C.BEXTI` (`shamt[4:0] != 0`) ✅
- `QC.C.SYNCWF` (`shamt[4:0] == 0`) (hint-compatible) ✅
- `C.SRLI` with `shamt == 0` (HINT)
- `QC.C.SYNC` (hint-compatible) 🔺Encoding not designated for custom use.
- `C.SRAI` with `shamt[5] == 1` (custom on rv32)
- `QC.C.BSETI` (`shamt[4:0] != 0`) ✅
- `QC.C.SYNCWL` (`shamt[4:0] == 0`) (hint-compatible) ✅
- `C.SRAI` with `shamt == 0` (HINT)
- `QC.C.SYNC` (hint-compatible) 🔺Encoding not designated for custom use.
- `C.SLLI` with `shamt[5] == 1` and `rd != x0` (custom on rv32 ✅)
- `QC.C.BEXTI`
- `QC.C.BSETI`
- `QC.C.EXTU`
- `QC.C.DIR`
- `QC.C.EIR`
- `QC.C.SETINT`
- `QC.C.CLRINT`
- `QC.C.MIENTER`
- `QC.C.MIENTER.NEST`
- `QC.C.MRET`
- `QC.C.MNRET`
- `QC.C.MILEAVERET`
- `QC.C.DI`
- `QC.C.EI`
- `C.SLLI` with `rd == x0` (`shamt[5] == 0`) (HINT)
- `QC.C.DELAY` (hint-compatible) ✅
- `QC.C.PTRACE` (hint-compatible) ✅
We are using some of the standard space, but in a hint-compatible way, and there are other places where we overlap e.g. `C.FSDSP`, `C.FLDSP`, and the `Zcmp` instructions already.
So I think broadly we're fine.
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