| Issue |
145360
|
| Summary |
rem/div-related miscompile from riscv64 and aarch64 backends
|
| Labels |
backend:AArch64,
backend:RISC-V,
miscompilation
|
| Assignees |
|
| Reporter |
regehr
|
I believe we're lowering this incorrectly:
```llvm
define i32 @f(i32 %0, ptr %1) {
%3 = srem i32 %0, 256
store i32 %3, ptr %1, align 4
%4 = sdiv exact i32 %0, 256
ret i32 %4
}
```
let's invoke `f` with `%0=2` and `%1` being a valid pointer to 4 bytes. in this case we should store 2 into memory and then return poison.
however, from the riscv64+m backend we get:
```
f:
sraiw a0, a0, 8
sw zero, 0(a1)
ret
```
the aarch64 output is functionally identical
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