Author: Jan Patrick Lehr Date: 2026-03-02T13:11:13+01:00 New Revision: f5c15702c28d6535fa8c947df465a917af09147c
URL: https://github.com/llvm/llvm-project/commit/f5c15702c28d6535fa8c947df465a917af09147c DIFF: https://github.com/llvm/llvm-project/commit/f5c15702c28d6535fa8c947df465a917af09147c.diff LOG: Revert "[VPlan] Remove unused VPExpandSCEVRecipe before expansion (#181329)" This reverts commit c62c00c52405da2650512ab030bef30a9ccaec6a. Added: Modified: llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp llvm/test/Transforms/LoopVectorize/cast-induction.ll llvm/test/Transforms/LoopVectorize/pointer-induction.ll llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll llvm/test/Transforms/LoopVectorize/version-mem-access.ll llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll Removed: ################################################################################ diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index c6aabe7f1ec0f..38b4c8bbae982 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -5130,10 +5130,6 @@ VPlanTransforms::expandSCEVs(VPlan &Plan, ScalarEvolution &SE) { auto *ExpSCEV = dyn_cast<VPExpandSCEVRecipe>(&R); if (!ExpSCEV) break; - if (ExpSCEV->getNumUsers() == 0) { - ExpSCEV->eraseFromParent(); - continue; - } const SCEV *Expr = ExpSCEV->getSCEV(); Value *Res = Expander.expandCodeFor(Expr, Expr->getType(), EntryBB->getTerminator()); diff --git a/llvm/test/Transforms/LoopVectorize/cast-induction.ll b/llvm/test/Transforms/LoopVectorize/cast-induction.ll index bcc2aea0f81ad..2764a61728fe3 100644 --- a/llvm/test/Transforms/LoopVectorize/cast-induction.ll +++ b/llvm/test/Transforms/LoopVectorize/cast-induction.ll @@ -322,6 +322,7 @@ define void @test_start_zext(i32 %start, ptr %dst) { ; VF4-SAME: i32 [[START:%.*]], ptr [[DST:%.*]]) { ; VF4-NEXT: [[ENTRY:.*:]] ; VF4-NEXT: [[START_EXT:%.*]] = zext i32 [[START]] to i64 +; VF4-NEXT: [[TMP0:%.*]] = sub i64 100, [[START_EXT]] ; VF4-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] ; VF4: [[VECTOR_SCEVCHECK]]: ; VF4-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[START]], 1 diff --git a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll index c73f2f7c865af..d5088fe60ee9f 100644 --- a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll +++ b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll @@ -713,10 +713,12 @@ define void @strided_ptr_iv_runtime_stride(ptr %pIn, ptr %pOut, i32 %nCols, i32 ; STRIDED-NEXT: [[POUT1:%.*]] = ptrtoaddr ptr [[POUT:%.*]] to i64 ; STRIDED-NEXT: [[TMP0:%.*]] = zext i32 [[NCOLS:%.*]] to i64 ; STRIDED-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1) +; STRIDED-NEXT: [[TMP1:%.*]] = sext i32 [[STRIDE:%.*]] to i64 +; STRIDED-NEXT: [[TMP2:%.*]] = shl nsw i64 [[TMP1]], 2 ; STRIDED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4 ; STRIDED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] ; STRIDED: vector.scevcheck: -; STRIDED-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STRIDE:%.*]], 1 +; STRIDED-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STRIDE]], 1 ; STRIDED-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]] ; STRIDED: vector.memcheck: ; STRIDED-NEXT: [[TMP3:%.*]] = sub i64 [[POUT1]], [[PIN2]] diff --git a/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll index b306dac8a4334..55c73cb0928ff 100644 --- a/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll +++ b/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll @@ -205,10 +205,21 @@ define void @expand_ diff _scev_unknown(ptr %dst, i1 %invar.c, i32 %step) mustprog ; CHECK-NEXT: br i1 [[INVAR_C]], label %[[LOOP_2_PREHEADER:.*]], label %[[LOOP_1]] ; CHECK: [[LOOP_2_PREHEADER]]: ; CHECK-NEXT: [[IV_1_LCSSA:%.*]] = phi i32 [ [[IV_1]], %[[LOOP_1]] ] +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[IV_1_LCSSA]], [[STEP]] +; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP1]], i32 0) +; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[STEP]], -2 +; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[INDVAR]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[SMAX]], [[TMP4]] +; CHECK-NEXT: [[UMIN:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP5]], i32 1) +; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[UMIN]], 1 +; CHECK-NEXT: [[TMP7:%.*]] = sub i32 [[TMP5]], [[UMIN]] +; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[STEP]], i32 1) +; CHECK-NEXT: [[TMP8:%.*]] = udiv i32 [[TMP7]], [[UMAX]] +; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP16:%.*]] = sub i32 2, [[STEP]] ; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[IV_1_LCSSA]], [[TMP16]] ; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP12]], i32 0) -; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[INDVAR]], -1 ; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP3]], -1 ; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[SMAX1]], [[TMP14]] ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP15]], 2 diff --git a/llvm/test/Transforms/LoopVectorize/version-mem-access.ll b/llvm/test/Transforms/LoopVectorize/version-mem-access.ll index baefa12858eb2..8b9a526899041 100644 --- a/llvm/test/Transforms/LoopVectorize/version-mem-access.ll +++ b/llvm/test/Transforms/LoopVectorize/version-mem-access.ll @@ -77,6 +77,7 @@ define void @fn1(ptr noalias %x, ptr noalias %c, double %a) { ; CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[CONV2]], 0 ; CHECK-NEXT: br i1 [[CMP8]], label %[[LOOP_PREHEADER:.*]], [[EXIT:label %.*]] ; CHECK: [[LOOP_PREHEADER]]: +; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[CONV2]] to i64 ; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] ; CHECK: [[VECTOR_SCEVCHECK]]: ; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[CONV]], 1 diff --git a/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll b/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll index 5839b0a5e8113..6a6ae316f4e52 100644 --- a/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll +++ b/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll @@ -401,6 +401,8 @@ define void @zext_of_i1_stride(i1 %g, ptr %dst) mustprogress { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[G_16:%.*]] = zext i1 [[G]] to i16 ; CHECK-NEXT: [[G_64:%.*]] = zext i1 [[G]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 15, [[G_64]] +; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 1 ; CHECK-NEXT: br label [[VECTOR_SCEVCHECK:%.*]] ; CHECK: vector.scevcheck: ; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i1 [[G]], true diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll index 51446cbbc51a9..8d20a3ba8ed08 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll @@ -66,7 +66,7 @@ define void @s172(i32 noundef %xa, i32 noundef %xb, ptr noundef %a, ptr noundef ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP8]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END]], label [[FOR_BODY_PREHEADER13]] -; CHECK: for.body.preheader11: +; CHECK: for.body.preheader14: ; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ [[TMP0]], [[VECTOR_MEMCHECK]] ], [ [[TMP0]], [[FOR_BODY_PREHEADER]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
