================
@@ -897,18 +897,27 @@ defm TLBIP : TLBITableBase;
multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4>
crm,
bits<3> op2, bit needsreg = 1, bit optionalreg = 0> {
+ defvar HasE1IS = !ne(!find(name, "E1IS"), -1);
+ defvar HasE1OS = !ne(!find(name, "E1OS"), -1);
+ defvar HasE2IS = !ne(!find(name, "E2IS"), -1);
+ defvar HasE2OS = !ne(!find(name, "E2OS"), -1);
+ defvar allowTLBID = !or(!or(HasE1IS, HasE1OS), !or(HasE2IS, HasE2OS));
----------------
jthackray wrote:
So I resisted adding an extra column to the monster table in
`llvm/lib/Target/AArch64/AArch64SystemOperands.td` from line 927 onwards, since
it ought to be possible to match the instructions at compile time. Yes, it's
ugly tablegen to do the match - ideally tablegen would allow a regex.
I'll see what I can do to improve this code; will come and chat with you, or
perhaps you can explain your idea a bit more here. Thanks.
https://github.com/llvm/llvm-project/pull/178913
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