https://github.com/jthackray created https://github.com/llvm/llvm-project/pull/177334
For FEAT_FPRCVT instructions, allow them to run in streaming mode if safe >From 79cbbac60dbdfed6f2f1b2815a890c96aa6a6a59 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Thu, 8 Jan 2026 16:08:36 +0000 Subject: [PATCH] [AArch64][llvm] Allow FPRCVT insns to run in streaming mode if safe For FEAT_FPRCVT instructions, allow them to run in streaming mode if safe --- .../Target/AArch64/AArch64ISelLowering.cpp | 3 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +- .../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 126 +++++------------- .../CodeGen/AArch64/arm64-cvtf-simd-itofp.ll | 30 ++--- 4 files changed, 49 insertions(+), 114 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 0fff8f52d6632..a5b18ac7cabca 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -20409,6 +20409,9 @@ tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG, N->getOpcode() == ISD::FP_TO_UINT_SAT) return SDValue(); + if (Subtarget->isStreaming() && Subtarget->hasFPRCVT()) + return SDValue(); + if (!Subtarget->isSVEorStreamingSVEAvailable() || (!Subtarget->isStreaming() && !Subtarget->isStreamingCompatible())) return SDValue(); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 59a3b2d36e0f0..9ce89e83b9a26 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -5318,7 +5318,7 @@ defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>; defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>; defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>; -let Predicates = [HasNEON, HasFPRCVT] in{ +let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in{ defm FCVTAS : FPToIntegerSIMDScalar<0b11, 0b010, "fcvtas", int_aarch64_neon_fcvtas>; defm FCVTAU : FPToIntegerSIMDScalar<0b11, 0b011, "fcvtau", int_aarch64_neon_fcvtau>; defm FCVTMS : FPToIntegerSIMDScalar<0b10, 0b100, "fcvtms", int_aarch64_neon_fcvtms>; @@ -5361,7 +5361,7 @@ def : Pat<(i64 (any_llround f64:$Rn)), defm SCVTF : IntegerToFP<0b00, 0b010, "scvtf", any_sint_to_fp>; defm UCVTF : IntegerToFP<0b00, 0b011, "ucvtf", any_uint_to_fp>; -let Predicates = [HasNEON, HasFPRCVT] in { +let Predicates = [HasNEONandIsStreamingSafe, HasFPRCVT] in { defm SCVTF : IntegerToFPSIMDScalar<0b11, 0b100, "scvtf", any_sint_to_fp>; defm UCVTF : IntegerToFPSIMDScalar<0b11, 0b101, "ucvtf", any_uint_to_fp>; diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll index 98bd2bc46a7ff..de7ddae5256e7 100644 --- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll +++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll @@ -36,8 +36,7 @@ define float @test_fptosi_f16_i32_simd(half %a) { ; ; CHECK-SME-LABEL: test_fptosi_f16_i32_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.h +; CHECK-SME-NEXT: fcvtzs s0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd: @@ -66,8 +65,7 @@ define double @test_fptosi_f16_i64_simd(half %a) { ; ; CHECK-SME-LABEL: test_fptosi_f16_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.h +; CHECK-SME-NEXT: fcvtzs d0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd: @@ -122,8 +120,7 @@ define double @test_fptosi_f32_i64_simd(float %a) { ; ; CHECK-SME-LABEL: test_fptosi_f32_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd: @@ -151,8 +148,7 @@ define double @test_fptosi_f64_i64_simd(double %a) { ; ; CHECK-SME-LABEL: test_fptosi_f64_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtzs d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd: @@ -181,8 +177,7 @@ define float @test_fptosi_f32_i32_simd(float %a) { ; ; CHECK-SME-LABEL: test_fptosi_f32_i32_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd: @@ -211,8 +206,7 @@ define float @test_fptoui_f16_i32_simd(half %a) { ; ; CHECK-SME-LABEL: test_fptoui_f16_i32_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.h +; CHECK-SME-NEXT: fcvtzu s0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd: @@ -241,8 +235,7 @@ define double @test_fptoui_f16_i64_simd(half %a) { ; ; CHECK-SME-LABEL: test_fptoui_f16_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.h +; CHECK-SME-NEXT: fcvtzu d0, h0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd: @@ -297,8 +290,7 @@ define double @test_fptoui_f32_i64_simd(float %a) { ; ; CHECK-SME-LABEL: test_fptoui_f32_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd: @@ -326,8 +318,7 @@ define double @test_fptoui_f64_i64_simd(double %a) { ; ; CHECK-SME-LABEL: test_fptoui_f64_i64_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtzu d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd: @@ -356,8 +347,7 @@ define float @test_fptoui_f32_i32_simd(float %a) { ; ; CHECK-SME-LABEL: test_fptoui_f32_i32_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzu s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd: @@ -706,9 +696,7 @@ define double @fcvtas_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtas_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtas d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtas_ds_round_simd: @@ -764,9 +752,7 @@ define float @fcvtas_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtas_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtas s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtas_ss_round_simd: @@ -795,9 +781,7 @@ define double @fcvtas_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtas_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtas d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtas_dd_round_simd: @@ -828,9 +812,7 @@ define double @fcvtau_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtau_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtau d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtau_ds_round_simd: @@ -886,9 +868,7 @@ define float @fcvtau_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtau_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtas s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtau_ss_round_simd: @@ -917,9 +897,7 @@ define double @fcvtau_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtau_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frinta d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtas d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtau_dd_round_simd: @@ -950,9 +928,7 @@ define double @fcvtms_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtms_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtms d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtms_ds_round_simd: @@ -1008,9 +984,7 @@ define float @fcvtms_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtms_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtms s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtms_ss_round_simd: @@ -1039,9 +1013,7 @@ define double @fcvtms_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtms_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtms d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtms_dd_round_simd: @@ -1073,9 +1045,7 @@ define double @fcvtmu_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtmu_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtmu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtmu_ds_round_simd: @@ -1131,9 +1101,7 @@ define float @fcvtmu_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtmu_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtms s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtmu_ss_round_simd: @@ -1162,9 +1130,7 @@ define double @fcvtmu_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtmu_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintm d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtms d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtmu_dd_round_simd: @@ -1195,9 +1161,7 @@ define double @fcvtps_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtps_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtps d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtps_ds_round_simd: @@ -1253,9 +1217,7 @@ define float @fcvtps_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtps_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtps s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtps_ss_round_simd: @@ -1284,9 +1246,7 @@ define double @fcvtps_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtps_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtps d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtps_dd_round_simd: @@ -1317,9 +1277,7 @@ define double @fcvtpu_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtpu_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtpu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtpu_ds_round_simd: @@ -1375,9 +1333,7 @@ define float @fcvtpu_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtpu_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtps s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtpu_ss_round_simd: @@ -1406,9 +1362,7 @@ define double @fcvtpu_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtpu_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintp d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtps d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtpu_dd_round_simd: @@ -1439,9 +1393,7 @@ define double @fcvtzs_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzs_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_ds_round_simd: @@ -1497,9 +1449,7 @@ define float @fcvtzs_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzs_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_ss_round_simd: @@ -1528,9 +1478,7 @@ define double @fcvtzs_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtzs_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtzs d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzs_dd_round_simd: @@ -1560,9 +1508,7 @@ define double @fcvtzu_ds_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzu_ds_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz s0, s0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzu d0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_ds_round_simd: @@ -1618,9 +1564,7 @@ define float @fcvtzu_ss_round_simd(float %a) { ; ; CHECK-SME-LABEL: fcvtzu_ss_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz s0, s0 -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s +; CHECK-SME-NEXT: fcvtzs s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_ss_round_simd: @@ -1649,9 +1593,7 @@ define double @fcvtzu_dd_round_simd(double %a) { ; ; CHECK-SME-LABEL: fcvtzu_dd_round_simd: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: frintz d0, d0 -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d +; CHECK-SME-NEXT: fcvtzs d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: fcvtzu_dd_round_simd: diff --git a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll index ab7d880b0d8e6..44594fad93d08 100644 --- a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll +++ b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll @@ -51,8 +51,7 @@ define half @scvtf_bitcast_f32_to_f16(float %f) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f16: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: scvtf z0.h, p0/m, z0.s +; CHECK-SME-NEXT: scvtf h0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f16: @@ -75,8 +74,7 @@ define half @ucvtf_bitcast_f32_to_f16(float %f) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f16: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: ucvtf z0.h, p0/m, z0.s +; CHECK-SME-NEXT: ucvtf h0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f16: @@ -99,8 +97,7 @@ define float @scvtf_bitcast_f64_to_f32(double %d) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f32: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: scvtf z0.s, p0/m, z0.d +; CHECK-SME-NEXT: scvtf s0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f32: @@ -123,8 +120,7 @@ define float @ucvtf_bitcast_f64_to_f32(double %d) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f32: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: ucvtf z0.s, p0/m, z0.d +; CHECK-SME-NEXT: ucvtf s0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f32: @@ -147,8 +143,7 @@ define half @scvtf_bitcast_f64_to_f16(double %d) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f16: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: scvtf z0.h, p0/m, z0.d +; CHECK-SME-NEXT: scvtf h0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f16: @@ -171,8 +166,7 @@ define half @ucvtf_bitcast_f64_to_f16(double %d) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f16: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: ucvtf z0.h, p0/m, z0.d +; CHECK-SME-NEXT: ucvtf h0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f16: @@ -195,8 +189,7 @@ define float @scvtf_bitcast_f32_to_f32(float %f) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f32: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: scvtf z0.s, p0/m, z0.s +; CHECK-SME-NEXT: scvtf s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f32: @@ -219,8 +212,7 @@ define float @ucvtf_bitcast_f32_to_f32(float %f) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f32: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.s -; CHECK-SME-NEXT: ucvtf z0.s, p0/m, z0.s +; CHECK-SME-NEXT: ucvtf s0, s0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f32: @@ -243,8 +235,7 @@ define double @scvtf_bitcast_f64_to_f64(double %d) nounwind { ; ; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f64: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: scvtf z0.d, p0/m, z0.d +; CHECK-SME-NEXT: scvtf d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f64: @@ -267,8 +258,7 @@ define double @ucvtf_bitcast_f64_to_f64(double %d) nounwind { ; ; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f64: ; CHECK-SME: // %bb.0: -; CHECK-SME-NEXT: ptrue p0.d -; CHECK-SME-NEXT: ucvtf z0.d, p0/m, z0.d +; CHECK-SME-NEXT: ucvtf d0, d0 ; CHECK-SME-NEXT: ret ; ; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f64: _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
