https://github.com/vangthao95 updated https://github.com/llvm/llvm-project/pull/176596
>From a93734b78b8968b34695873f5c7277a10b2b0ea5 Mon Sep 17 00:00:00 2001 From: Vang Thao <[email protected]> Date: Sat, 17 Jan 2026 14:04:56 -0800 Subject: [PATCH 1/2] [AMDGPU][GlobalISel] Add RegBankLegalize rules for SMED3 and CVT_PK_I16_I32 These opcodes are created together for the i64->i16 signed clamp pattern. --- .../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 8 ++++ .../AMDGPU/GlobalISel/combine-short-clamp.ll | 8 ++-- .../regbankselect-amdgpu-cvt-pk-i16-i32.mir | 41 +++++++++++++++++ .../GlobalISel/regbankselect-amdgpu-smed3.mir | 46 +++++++++++++++++++ 4 files changed, 99 insertions(+), 4 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-cvt-pk-i16-i32.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-smed3.mir diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index ce80a94f29222..def076525c470 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -1060,6 +1060,14 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}}) .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}}); + addRulesForGOpcs({G_AMDGPU_SMED3}, Standard) + .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}}) + .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}}); + + addRulesForGOpcs({G_AMDGPU_CVT_PK_I16_I32}, Standard) + .Uni(V2S16, {{UniInVgprV2S16}, {Vgpr32, Vgpr32}}) + .Div(V2S16, {{VgprV2S16}, {Vgpr32, Vgpr32}}); + // FNEG and FABS are either folded as source modifiers or can be selected as // bitwise XOR and AND with Mask. XOR and AND are available on SALU but for // targets without SALU float we still select them as VGPR since there would diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll index 7db49bca36062..d356153fe7360 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX678 %s -; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX9 %s -; RUN: llc -global-isel -mcpu=gfx1010 -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GFX10 %s -; RUN: llc -global-isel -mcpu=gfx1100 -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GFX11 %s +; RUN: llc -global-isel -new-reg-bank-select -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX678 %s +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck --check-prefixes=GCN,GFX9 %s +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1010 -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GFX10 %s +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1100 -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GFX11 %s declare i64 @llvm.smax.i64(i64, i64) declare i64 @llvm.smin.i64(i64, i64) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-cvt-pk-i16-i32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-cvt-pk-i16-i32.mir new file mode 100644 index 0000000000000..656f5a2fc1e05 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-cvt-pk-i16-i32.mir @@ -0,0 +1,41 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s + +--- +name: cvt_pk_i16_i32_ss +legalized: true + +body: | + bb.0: + liveins: $sgpr0, $sgpr1 + ; CHECK-LABEL: name: cvt_pk_i16_i32_ss + ; CHECK: liveins: $sgpr0, $sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[AMDGPU_CVT_PK_I16_I32_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_CVT_PK_I16_I32 [[COPY2]], [[COPY3]] + ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(<2 x s16>) = G_AMDGPU_READANYLANE [[AMDGPU_CVT_PK_I16_I32_]] + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:_(<2 x s16>) = G_AMDGPU_CVT_PK_I16_I32 %0, %1 +... + +--- +name: cvt_pk_i16_i32_vv +legalized: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: cvt_pk_i16_i32_vv + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[AMDGPU_CVT_PK_I16_I32_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_CVT_PK_I16_I32 [[COPY]], [[COPY1]] + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(<2 x s16>) = G_AMDGPU_CVT_PK_I16_I32 %0, %1 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-smed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-smed3.mir new file mode 100644 index 0000000000000..a29d0bc9063e8 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-smed3.mir @@ -0,0 +1,46 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s + +--- +name: smed3_sss +legalized: true + +body: | + bb.0: + liveins: $sgpr0, $sgpr1, $sgpr2 + ; CHECK-LABEL: name: smed3_sss + ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) + ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY3]], [[COPY4]], [[COPY5]] + ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[AMDGPU_SMED3_]] + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:_(s32) = COPY $sgpr2 + %3:_(s32) = G_AMDGPU_SMED3 %0, %1, %2 +... + +--- +name: smed3_vvv +legalized: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1, $vgpr2 + ; CHECK-LABEL: name: smed3_vvv + ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 + ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY1]], [[COPY2]] + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(s32) = G_AMDGPU_SMED3 %0, %1, %2 +... >From 2eba7de24806ae397fe6f2482ba2e97b6fa802d6 Mon Sep 17 00:00:00 2001 From: Vang Thao <[email protected]> Date: Mon, 19 Jan 2026 11:06:59 -0800 Subject: [PATCH 2/2] Add uniform clamp test, remove *.mir tests, move CVT opcode. --- .../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 11 +++-- .../AMDGPU/GlobalISel/combine-short-clamp.ll | 44 ++++++++++++++++++ .../regbankselect-amdgpu-cvt-pk-i16-i32.mir | 41 ----------------- .../GlobalISel/regbankselect-amdgpu-smed3.mir | 46 ------------------- 4 files changed, 51 insertions(+), 91 deletions(-) delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-cvt-pk-i16-i32.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-smed3.mir diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index def076525c470..8d45e11e1c8e1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -1060,14 +1060,13 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}}) .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}}); + // TODO: This opcode is generated from the i64->i16 signed clamped pattern in + // the PreLegalizerCombiner. Move the combine to RegBankCombiner to keep more + // instructions on SALU. addRulesForGOpcs({G_AMDGPU_SMED3}, Standard) .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}}) .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}}); - addRulesForGOpcs({G_AMDGPU_CVT_PK_I16_I32}, Standard) - .Uni(V2S16, {{UniInVgprV2S16}, {Vgpr32, Vgpr32}}) - .Div(V2S16, {{VgprV2S16}, {Vgpr32, Vgpr32}}); - // FNEG and FABS are either folded as source modifiers or can be selected as // bitwise XOR and AND with Mask. XOR and AND are available on SALU but for // targets without SALU float we still select them as VGPR since there would @@ -1115,6 +1114,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}}, hasSALUFloat) .Any({{UniS32, S16}, {{UniInVgprS32}, {Vgpr16}}}, !hasSALUFloat); + addRulesForGOpcs({G_AMDGPU_CVT_PK_I16_I32}, Standard) + .Uni(V2S16, {{UniInVgprV2S16}, {Vgpr32, Vgpr32}}) + .Div(V2S16, {{VgprV2S16}, {Vgpr32, Vgpr32}}); + addRulesForGOpcs({G_FPTRUNC}) .Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}}) .Any({{UniS32, S64}, {{UniInVgprS32}, {Vgpr64}}}) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll index d356153fe7360..7f186337e451c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll @@ -314,3 +314,47 @@ entry: %result = trunc i64 %min to i16 ret i16 %result } + +define i16 @clamp_i64_i16_uniform(i64 inreg %in) #0 { +; GFX678-LABEL: clamp_i64_i16_uniform: +; GFX678: ; %bb.0: ; %entry +; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX678-NEXT: v_mov_b32_e32 v0, s17 +; GFX678-NEXT: v_cvt_pk_i16_i32_e32 v0, s16, v0 +; GFX678-NEXT: v_mov_b32_e32 v1, 0xffff8000 +; GFX678-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX678-NEXT: v_med3_i32 v0, v1, v0, v2 +; GFX678-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: clamp_i64_i16_uniform: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s17 +; GFX9-NEXT: v_cvt_pk_i16_i32 v0, s16, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff8000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX9-NEXT: v_med3_i32 v0, v1, v0, v2 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: clamp_i64_i16_uniform: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cvt_pk_i16_i32 v0, s16, s17 +; GFX10-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX10-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: clamp_i64_i16_uniform: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cvt_pk_i16_i32 v0, s0, s1 +; GFX11-NEXT: v_mov_b32_e32 v1, 0x7fff +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_med3_i32 v0, 0xffff8000, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] +entry: + %max = call i64 @llvm.smax.i64(i64 %in, i64 -32768) + %min = call i64 @llvm.smin.i64(i64 %max, i64 32767) + %result = trunc i64 %min to i16 + ret i16 %result +} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-cvt-pk-i16-i32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-cvt-pk-i16-i32.mir deleted file mode 100644 index 656f5a2fc1e05..0000000000000 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-cvt-pk-i16-i32.mir +++ /dev/null @@ -1,41 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s - ---- -name: cvt_pk_i16_i32_ss -legalized: true - -body: | - bb.0: - liveins: $sgpr0, $sgpr1 - ; CHECK-LABEL: name: cvt_pk_i16_i32_ss - ; CHECK: liveins: $sgpr0, $sgpr1 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; CHECK-NEXT: [[AMDGPU_CVT_PK_I16_I32_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_CVT_PK_I16_I32 [[COPY2]], [[COPY3]] - ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(<2 x s16>) = G_AMDGPU_READANYLANE [[AMDGPU_CVT_PK_I16_I32_]] - %0:_(s32) = COPY $sgpr0 - %1:_(s32) = COPY $sgpr1 - %2:_(<2 x s16>) = G_AMDGPU_CVT_PK_I16_I32 %0, %1 -... - ---- -name: cvt_pk_i16_i32_vv -legalized: true - -body: | - bb.0: - liveins: $vgpr0, $vgpr1 - ; CHECK-LABEL: name: cvt_pk_i16_i32_vv - ; CHECK: liveins: $vgpr0, $vgpr1 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 - ; CHECK-NEXT: [[AMDGPU_CVT_PK_I16_I32_:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_CVT_PK_I16_I32 [[COPY]], [[COPY1]] - %0:_(s32) = COPY $vgpr0 - %1:_(s32) = COPY $vgpr1 - %2:_(<2 x s16>) = G_AMDGPU_CVT_PK_I16_I32 %0, %1 -... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-smed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-smed3.mir deleted file mode 100644 index a29d0bc9063e8..0000000000000 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-smed3.mir +++ /dev/null @@ -1,46 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s - ---- -name: smed3_sss -legalized: true - -body: | - bb.0: - liveins: $sgpr0, $sgpr1, $sgpr2 - ; CHECK-LABEL: name: smed3_sss - ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) - ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY3]], [[COPY4]], [[COPY5]] - ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[AMDGPU_SMED3_]] - %0:_(s32) = COPY $sgpr0 - %1:_(s32) = COPY $sgpr1 - %2:_(s32) = COPY $sgpr2 - %3:_(s32) = G_AMDGPU_SMED3 %0, %1, %2 -... - ---- -name: smed3_vvv -legalized: true - -body: | - bb.0: - liveins: $vgpr0, $vgpr1, $vgpr2 - ; CHECK-LABEL: name: smed3_vvv - ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 - ; CHECK-NEXT: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[COPY1]], [[COPY2]] - %0:_(s32) = COPY $vgpr0 - %1:_(s32) = COPY $vgpr1 - %2:_(s32) = COPY $vgpr2 - %3:_(s32) = G_AMDGPU_SMED3 %0, %1, %2 -... _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
