Author: Craig Topper Date: 2026-01-13T10:18:54Z New Revision: afcbb8bac78689c58b4f85f493ebcfb0ecb8a0b7
URL: https://github.com/llvm/llvm-project/commit/afcbb8bac78689c58b4f85f493ebcfb0ecb8a0b7 DIFF: https://github.com/llvm/llvm-project/commit/afcbb8bac78689c58b4f85f493ebcfb0ecb8a0b7.diff LOG: [RISCV] Sync Inst{30-27} assignment into RVPWideningBase. NFC (#175705) 2 of the 3 subclases can pass 'f' straight through from their instantiations. The third case just needs to concatenate 1b1 to widen f to 4 bits. Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoP.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index 8b7b537bc0a73..959c0f1d36e30 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -106,7 +106,7 @@ class PLUI_i<bits<7> funct7, string opcodestr> } // Common base for widening Binary/Ternary ops -class RVPWideningBase<bits<2> w, bit arith_shift, dag outs, dag ins, +class RVPWideningBase<bits<4> f, bits<2> w, bit arith_shift, dag outs, dag ins, string opcodestr> : RVInst<outs, ins, opcodestr, "$rd, $rs1, $rs2", [], InstFormatOther> { bits<5> rs2; @@ -114,6 +114,7 @@ class RVPWideningBase<bits<2> w, bit arith_shift, dag outs, dag ins, bits<5> rd; let Inst{31} = 0b0; + let Inst{30-27} = f; let Inst{26-25} = w; let Inst{24-20} = rs2; let Inst{19-15} = rs1; @@ -332,11 +333,8 @@ class RVPNarrowingShift_rr<bits<3> f, bits<2> w, string opcodestr> let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class RVPWideningShift_rr<bits<3> f, bits<2> w, string opcodestr> - : RVPWideningBase<w, 0b0, (outs GPRPairRV32:$rd), (ins GPR:$rs1, GPR:$rs2), - opcodestr> { - let Inst{30-28} = f; - let Inst{27} = 0b1; -} + : RVPWideningBase<{f, 0b1}, w, 0b0, (outs GPRPairRV32:$rd), + (ins GPR:$rs1, GPR:$rs2), opcodestr>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class RVPPairShift_rr<bits<3> f, bits<2> w, string opcodestr, @@ -393,10 +391,8 @@ class RVPBinary_rr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr, let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class RVPWideningBinary_rr<bits<4> f, bits<2> w, string opcodestr, bit Commutable = 0> - : RVPWideningBase<w, 0b1, (outs GPRPairRV32:$rd), (ins GPR:$rs1, GPR:$rs2), - opcodestr> { - let Inst{30-27} = f; - + : RVPWideningBase<f, w, 0b1, (outs GPRPairRV32:$rd), + (ins GPR:$rs1, GPR:$rs2), opcodestr> { let isCommutable = Commutable; } @@ -447,10 +443,8 @@ class RVPTernary_rrr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr> let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class RVPWideningTernary_rrr<bits<4> f, bits<2> w, string opcodestr> - : RVPWideningBase<w, 0b1, (outs GPRPairRV32:$rd_wb), - (ins GPRPairRV32:$rd, GPR:$rs1, GPR:$rs2), opcodestr> { - let Inst{30-27} = f; - + : RVPWideningBase<f, w, 0b1, (outs GPRPairRV32:$rd_wb), + (ins GPRPairRV32:$rd, GPR:$rs1, GPR:$rs2), opcodestr> { let Constraints = "$rd = $rd_wb"; } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
