https://github.com/slinder1 updated https://github.com/llvm/llvm-project/pull/164726
>From 314c97af1950e9ddedaa0e2a615fae7ebfe3309e Mon Sep 17 00:00:00 2001 From: Emma Pilkington <[email protected]> Date: Thu, 19 Jun 2025 11:00:27 -0400 Subject: [PATCH] [AMDGPU][MC] Replace shifted registers in CFI instructions --- llvm/include/llvm/CodeGen/MachineFunction.h | 4 + llvm/include/llvm/MC/MCDwarf.h | 3 + llvm/lib/CodeGen/MachineFunction.cpp | 10 ++ llvm/lib/MC/MCDwarf.cpp | 33 +++++ .../Target/AMDGPU/SIMachineFunctionInfo.cpp | 3 + llvm/test/CodeGen/AMDGPU/debug-frame.ll | 8 +- .../AMDGPU/dwarf-multi-register-use-crash.ll | 30 ++-- .../CodeGen/AMDGPU/insert-waitcnts-crash.ll | 2 +- .../AMDGPU/no-source-locations-in-prologue.ll | 2 +- .../AMDGPU/sgpr-spill-overlap-wwm-reserve.mir | 134 +++++++++--------- 10 files changed, 141 insertions(+), 88 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index ef783f276b7d4..5db370c160ce3 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -1234,6 +1234,10 @@ class LLVM_ABI MachineFunction { [[nodiscard]] unsigned addFrameInst(const MCCFIInstruction &Inst); + /// Replace all references to register \param From with register \param To in + /// frame instructions. Note that .cfi_escape instructions will be left as-is. + void replaceFrameInstRegister(Register From, Register To); + /// Returns a reference to a list of symbols immediately following calls to /// _setjmp in the function. Used to construct the longjmp target table used /// by Windows Control Flow Guard. diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h index e602f03de5ebf..9df687c282a0c 100644 --- a/llvm/include/llvm/MC/MCDwarf.h +++ b/llvm/include/llvm/MC/MCDwarf.h @@ -837,6 +837,9 @@ class MCCFIInstruction { return std::get<EscapeFields>(ExtraFields).Comment; } SMLoc getLoc() const { return Loc; } + + /// Replaces in place all references to FromReg with ToReg. + void replaceRegister(unsigned FromReg, unsigned ToReg); }; struct MCDwarfFrameInfo { diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index bfa5ab274c686..69836ef27f8c3 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -336,6 +336,16 @@ MachineFunction::addFrameInst(const MCCFIInstruction &Inst) { return FrameInstructions.size() - 1; } +void MachineFunction::replaceFrameInstRegister(Register FromReg, + Register ToReg) { + const MCRegisterInfo *MCRI = Ctx.getRegisterInfo(); + unsigned DwarfFromReg = MCRI->getDwarfRegNum(FromReg, false); + unsigned DwarfToReg = MCRI->getDwarfRegNum(ToReg, false); + + for (MCCFIInstruction &Inst : FrameInstructions) + Inst.replaceRegister(DwarfFromReg, DwarfToReg); +} + /// This discards all of the MachineBasicBlock numbers and recomputes them. /// This guarantees that the MBB numbers are sequential, dense, and match the /// ordering of the blocks within the function. If a specific MachineBasicBlock diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp index 09a93dd34ece3..b9d8783009376 100644 --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -1292,6 +1292,39 @@ void MCGenDwarfLabelEntry::Make(MCSymbol *Symbol, MCStreamer *MCOS, MCGenDwarfLabelEntry(Name, FileNumber, LineNumber, Label)); } +void MCCFIInstruction::replaceRegister(unsigned FromReg, unsigned ToReg) { + auto ReplaceReg = [=](unsigned &Reg) { + if (Reg == FromReg) + Reg = ToReg; + }; + auto Visitor = makeVisitor( + [=](CommonFields &F) { + ReplaceReg(F.Register); + ReplaceReg(F.Register2); + }, + [](EscapeFields &) {}, [](LabelFields &) {}, + [=](RegisterPairFields &F) { + ReplaceReg(F.Register); + ReplaceReg(F.Reg1); + ReplaceReg(F.Reg2); + }, + [=](VectorRegistersFields &F) { + ReplaceReg(F.Register); + for (auto &VRL : F.VectorRegisters) + ReplaceReg(VRL.Register); + }, + [=](VectorOffsetFields &F) { + ReplaceReg(F.Register); + ReplaceReg(F.MaskRegister); + }, + [=](VectorRegisterMaskFields &F) { + ReplaceReg(F.Register); + ReplaceReg(F.SpillRegister); + ReplaceReg(F.MaskRegister); + }); + std::visit(Visitor, ExtraFields); +} + static int getDataAlignmentFactor(MCStreamer &streamer) { MCContext &context = streamer.getContext(); const MCAsmInfo *asmInfo = context.getAsmInfo(); diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 770398f428417..57c675f04ad94 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -386,6 +386,9 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange( if (RegItr != SpillPhysVGPRs.end()) { unsigned Idx = std::distance(SpillPhysVGPRs.begin(), RegItr); SpillPhysVGPRs[Idx] = NewReg; + + // For replacing registers used in the CFI instructions. + MF.replaceFrameInstRegister(Reg, NewReg); } // The generic `determineCalleeSaves` might have set the old register if it diff --git a/llvm/test/CodeGen/AMDGPU/debug-frame.ll b/llvm/test/CodeGen/AMDGPU/debug-frame.ll index c3c93c1b606ec..5fa5452aba86e 100644 --- a/llvm/test/CodeGen/AMDGPU/debug-frame.ll +++ b/llvm/test/CodeGen/AMDGPU/debug-frame.ll @@ -2449,7 +2449,7 @@ define hidden void @func_call_clobber() #0 { ; GFX900-NEXT: v_writelane_b32 v40, s30, 0 ; GFX900-NEXT: s_addk_i32 s32, 0x400 ; GFX900-NEXT: v_writelane_b32 v40, s31, 1 -; GFX900-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32 +; GFX900-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32 ; GFX900-NEXT: s_getpc_b64 s[16:17] ; GFX900-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4 ; GFX900-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12 @@ -2723,7 +2723,7 @@ define hidden void @func_call_clobber() #0 { ; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s30, 0 ; GFX90A-V2A-DIS-NEXT: s_addk_i32 s32, 0x400 ; GFX90A-V2A-DIS-NEXT: v_writelane_b32 v40, s31, 1 -; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32 +; GFX90A-V2A-DIS-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32 ; GFX90A-V2A-DIS-NEXT: s_getpc_b64 s[16:17] ; GFX90A-V2A-DIS-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4 ; GFX90A-V2A-DIS-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12 @@ -2997,7 +2997,7 @@ define hidden void @func_call_clobber() #0 { ; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s30, 0 ; GFX90A-V2A-EN-NEXT: s_addk_i32 s32, 0x400 ; GFX90A-V2A-EN-NEXT: v_writelane_b32 v40, s31, 1 -; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 16, 2815, 0, 32, 2815, 1, 32 +; GFX90A-V2A-EN-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32 ; GFX90A-V2A-EN-NEXT: s_getpc_b64 s[16:17] ; GFX90A-V2A-EN-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4 ; GFX90A-V2A-EN-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12 @@ -3240,7 +3240,7 @@ define hidden void @func_call_clobber() #0 { ; WAVE32-NEXT: v_writelane_b32 v40, s30, 0 ; WAVE32-NEXT: s_addk_i32 s32, 0x200 ; WAVE32-NEXT: v_writelane_b32 v40, s31, 1 -; WAVE32-NEXT: .cfi_llvm_vector_registers 16, 1791, 0, 32, 1791, 1, 32 +; WAVE32-NEXT: .cfi_llvm_vector_registers 16, 1576, 0, 32, 1576, 1, 32 ; WAVE32-NEXT: s_getpc_b64 s[16:17] ; WAVE32-NEXT: s_add_u32 s16, s16, ex@rel32@lo+4 ; WAVE32-NEXT: s_addc_u32 s17, s17, ex@rel32@hi+12 diff --git a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll index bc928041ed750..51300c363e611 100644 --- a/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll @@ -493,36 +493,36 @@ define weak_odr void @test(i32 %0) !dbg !34 { ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CHECK-NEXT: .cfi_llvm_vector_offset 2600, 32, 17, 64, 0 ; CHECK-NEXT: v_writelane_b32 v41, s34, 0 -; CHECK-NEXT: .cfi_llvm_vector_registers 66, 2622, 0, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 66, 2601, 0, 32 ; CHECK-NEXT: v_writelane_b32 v41, s35, 1 -; CHECK-NEXT: .cfi_llvm_vector_registers 67, 2622, 1, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 67, 2601, 1, 32 ; CHECK-NEXT: v_writelane_b32 v41, s36, 2 -; CHECK-NEXT: .cfi_llvm_vector_registers 68, 2622, 2, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 68, 2601, 2, 32 ; CHECK-NEXT: v_writelane_b32 v41, s37, 3 -; CHECK-NEXT: .cfi_llvm_vector_registers 69, 2622, 3, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 69, 2601, 3, 32 ; CHECK-NEXT: v_writelane_b32 v41, s38, 4 -; CHECK-NEXT: .cfi_llvm_vector_registers 70, 2622, 4, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 70, 2601, 4, 32 ; CHECK-NEXT: v_writelane_b32 v41, s39, 5 -; CHECK-NEXT: .cfi_llvm_vector_registers 71, 2622, 5, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 71, 2601, 5, 32 ; CHECK-NEXT: v_writelane_b32 v41, s48, 6 -; CHECK-NEXT: .cfi_llvm_vector_registers 80, 2622, 6, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 80, 2601, 6, 32 ; CHECK-NEXT: v_writelane_b32 v41, s49, 7 -; CHECK-NEXT: .cfi_llvm_vector_registers 81, 2622, 7, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 81, 2601, 7, 32 ; CHECK-NEXT: v_writelane_b32 v41, s50, 8 -; CHECK-NEXT: .cfi_llvm_vector_registers 82, 2622, 8, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 82, 2601, 8, 32 ; CHECK-NEXT: v_writelane_b32 v41, s51, 9 -; CHECK-NEXT: .cfi_llvm_vector_registers 83, 2622, 9, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 83, 2601, 9, 32 ; CHECK-NEXT: v_writelane_b32 v41, s52, 10 -; CHECK-NEXT: .cfi_llvm_vector_registers 84, 2622, 10, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 84, 2601, 10, 32 ; CHECK-NEXT: v_writelane_b32 v41, s53, 11 -; CHECK-NEXT: .cfi_llvm_vector_registers 85, 2622, 11, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 85, 2601, 11, 32 ; CHECK-NEXT: v_writelane_b32 v41, s54, 12 -; CHECK-NEXT: .cfi_llvm_vector_registers 86, 2622, 12, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 86, 2601, 12, 32 ; CHECK-NEXT: v_writelane_b32 v41, s55, 13 -; CHECK-NEXT: .cfi_llvm_vector_registers 87, 2622, 13, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 87, 2601, 13, 32 ; CHECK-NEXT: v_writelane_b32 v41, s30, 14 ; CHECK-NEXT: v_writelane_b32 v41, s31, 15 -; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2622, 14, 32, 2622, 15, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2601, 14, 32, 2601, 15, 32 ; CHECK-NEXT: s_mov_b64 s[48:49], s[4:5] ; CHECK-NEXT: ;DEBUG_VALUE: dummy:dummy <- undef ; CHECK-NEXT: .Ltmp0: diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll index c1c69d9cb8f6e..3b367f4ae2fc0 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll @@ -19,7 +19,7 @@ define fastcc i32 @foo() #0 { ; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31 ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr127, 0, 32, $vgpr127, 1, 32 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr40, 0, 32, $vgpr40, 1, 32 ; CHECK-NEXT: BUNDLE implicit-def $sgpr16_sgpr17, implicit-def $sgpr16, implicit-def $scc, implicit-def $sgpr17 { ; CHECK-NEXT: $sgpr16_sgpr17 = S_GETPC_B64 ; CHECK-NEXT: $sgpr16 = S_ADD_U32 internal $sgpr16, target-flags(amdgpu-gotprel32-lo) @bar + 4, implicit-def $scc diff --git a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll index 10c4b825308e1..6154a170c7579 100644 --- a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll +++ b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll @@ -233,7 +233,7 @@ define hidden void @_ZL3barv() #0 !dbg !1644 { ; CHECK-NEXT: s_add_i32 s32, s32, 0x400 ; CHECK-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-NEXT: v_writelane_b32 v40, s31, 1 -; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2623, 0, 32, 2623, 1, 32 +; CHECK-NEXT: .cfi_llvm_vector_registers 16, 2600, 0, 32, 2600, 1, 32 ; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .loc 0 31 3 prologue_end ; lane-info.cpp:31:3 ; CHECK-NEXT: s_getpc_b64 s[16:17] diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir index 6488b44275f4e..4a63b44099b66 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir @@ -41,140 +41,140 @@ body: | ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 ; GCN-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr255, 0, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr4, $vgpr2, 0, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr5, $vgpr255, 1, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr5, $vgpr2, 1, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr6, 2, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr6, $vgpr255, 2, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr6, $vgpr2, 2, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr7, 3, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr7, $vgpr255, 3, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr7, $vgpr2, 3, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr8, 4, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr8, $vgpr255, 4, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr8, $vgpr2, 4, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr9, 5, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr9, $vgpr255, 5, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr9, $vgpr2, 5, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr10, 6, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr10, $vgpr255, 6, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr10, $vgpr2, 6, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr11, 7, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr11, $vgpr255, 7, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr11, $vgpr2, 7, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr12, 8, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr12, $vgpr255, 8, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr12, $vgpr2, 8, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr13, 9, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr13, $vgpr255, 9, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr13, $vgpr2, 9, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr14, 10, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr14, $vgpr255, 10, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr14, $vgpr2, 10, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr15, 11, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr15, $vgpr255, 11, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr15, $vgpr2, 11, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr16, 12, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr16, $vgpr255, 12, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr16, $vgpr2, 12, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr17, 13, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr17, $vgpr255, 13, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr17, $vgpr2, 13, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr18, 14, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr18, $vgpr255, 14, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr18, $vgpr2, 14, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr19, 15, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr19, $vgpr255, 15, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr19, $vgpr2, 15, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr20, 16, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr20, $vgpr255, 16, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr20, $vgpr2, 16, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr21, 17, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr21, $vgpr255, 17, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr21, $vgpr2, 17, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr22, 18, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr22, $vgpr255, 18, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr22, $vgpr2, 18, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr23, 19, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr23, $vgpr255, 19, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr23, $vgpr2, 19, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr24, 20, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr24, $vgpr255, 20, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr24, $vgpr2, 20, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr25, 21, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr25, $vgpr255, 21, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr25, $vgpr2, 21, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr26, 22, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr26, $vgpr255, 22, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr26, $vgpr2, 22, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr27, 23, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr27, $vgpr255, 23, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr27, $vgpr2, 23, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr28, 24, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr28, $vgpr255, 24, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr28, $vgpr2, 24, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr29, 25, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr29, $vgpr255, 25, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr29, $vgpr2, 25, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr64, 26, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr255, 26, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr64, $vgpr2, 26, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr65, 27, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr255, 27, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr65, $vgpr2, 27, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr66, 28, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr255, 28, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr66, $vgpr2, 28, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr67, 29, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr255, 29, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr67, $vgpr2, 29, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr68, 30, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr255, 30, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr68, $vgpr2, 30, 32 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr69, 31, $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr255, 31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr69, $vgpr2, 31, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr70, 0, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr70, $vgpr254, 0, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr70, $vgpr3, 0, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr71, 1, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr71, $vgpr254, 1, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr71, $vgpr3, 1, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr72, 2, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr72, $vgpr254, 2, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr72, $vgpr3, 2, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr73, 3, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr73, $vgpr254, 3, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr73, $vgpr3, 3, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr74, 4, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr74, $vgpr254, 4, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr74, $vgpr3, 4, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr75, 5, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr75, $vgpr254, 5, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr75, $vgpr3, 5, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr76, 6, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr76, $vgpr254, 6, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr76, $vgpr3, 6, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr77, 7, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr77, $vgpr254, 7, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr77, $vgpr3, 7, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr78, 8, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr78, $vgpr254, 8, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr78, $vgpr3, 8, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr79, 9, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr79, $vgpr254, 9, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr79, $vgpr3, 9, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr80, 10, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr80, $vgpr254, 10, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr80, $vgpr3, 10, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr81, 11, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr81, $vgpr254, 11, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr81, $vgpr3, 11, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr82, 12, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr82, $vgpr254, 12, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr82, $vgpr3, 12, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr83, 13, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr83, $vgpr254, 13, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr83, $vgpr3, 13, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr84, 14, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr84, $vgpr254, 14, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr84, $vgpr3, 14, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr85, 15, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr85, $vgpr254, 15, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr85, $vgpr3, 15, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr86, 16, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr86, $vgpr254, 16, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr86, $vgpr3, 16, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr87, 17, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr87, $vgpr254, 17, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr87, $vgpr3, 17, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr88, 18, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr88, $vgpr254, 18, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr88, $vgpr3, 18, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr89, 19, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr89, $vgpr254, 19, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr89, $vgpr3, 19, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr90, 20, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr90, $vgpr254, 20, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr90, $vgpr3, 20, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr91, 21, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr91, $vgpr254, 21, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr91, $vgpr3, 21, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr92, 22, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr92, $vgpr254, 22, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr92, $vgpr3, 22, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr93, 23, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr93, $vgpr254, 23, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr93, $vgpr3, 23, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr94, 24, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr94, $vgpr254, 24, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr94, $vgpr3, 24, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr95, 25, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr95, $vgpr254, 25, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr95, $vgpr3, 25, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr96, 26, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr96, $vgpr254, 26, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr96, $vgpr3, 26, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr97, 27, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr97, $vgpr254, 27, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr97, $vgpr3, 27, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr98, 28, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr98, $vgpr254, 28, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr98, $vgpr3, 28, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr99, 29, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr99, $vgpr254, 29, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr99, $vgpr3, 29, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr100, 30, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr100, $vgpr254, 30, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr100, $vgpr3, 30, 32 ; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr101, 31, $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr101, $vgpr254, 31, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr101, $vgpr3, 31, 32 ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr102, 0, $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr102, $vgpr253, 0, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr102, $vgpr4, 0, 32 ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr103, 1, $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr103, $vgpr253, 1, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr103, $vgpr4, 1, 32 ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr30, 2, $vgpr4, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31 ; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr31, 3, $vgpr4, implicit $sgpr30_sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr253, 2, 32, $vgpr253, 3, 32 + ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $pc_reg, $vgpr4, 2, 32, $vgpr4, 3, 32 ; GCN-NEXT: $sgpr22 = IMPLICIT_DEF ; GCN-NEXT: $vgpr5 = IMPLICIT_DEF ; GCN-NEXT: $vgpr5 = SI_SPILL_S32_TO_VGPR $sgpr22, 0, killed $vgpr5 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
