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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp --
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
``````````
:warning:
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 042380383..8b8a10964 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5396,7 +5396,7 @@ static bool is32bitWaveReduceOperation(unsigned Opc) {
}
static bool isFloatingPointWaveReduceOperation(unsigned Opc) {
- return Opc == AMDGPU::V_MIN_F32_e64 || Opc == AMDGPU::V_MAX_F32_e64 ||
+ return Opc == AMDGPU::V_MIN_F32_e64 || Opc == AMDGPU::V_MAX_F32_e64 ||
Opc == AMDGPU::V_ADD_F32_e64 || Opc == AMDGPU::V_SUB_F32_e64;
}
@@ -5446,7 +5446,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr
&MI,
case AMDGPU::S_ADD_U64_PSEUDO:
case AMDGPU::V_ADD_F32_e64:
case AMDGPU::S_SUB_I32:
- case AMDGPU::S_SUB_U64_PSEUDO:
+ case AMDGPU::S_SUB_U64_PSEUDO:
case AMDGPU::V_SUB_F32_e64: {
const TargetRegisterClass *WaveMaskRegClass = TRI->getWaveMaskRegClass();
const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg);
@@ -5604,33 +5604,38 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr
&MI,
}
case AMDGPU::V_ADD_F32_e64:
case AMDGPU::V_SUB_F32_e64: {
- /// for FPop: #activebits: int, src: float.
- /// convert int to float, and then mul. there is only V_MUL_F32, so copy
to vgpr.
- ///
/home/aalokdes/dockerx/work/llvm-trunk/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
- /// ig: 1(01) -> negation, 2(10) -> abs, 3(11) -> abs and neg
- // V_CVT_F32_I32_e64
- // get #active lanes in vgpr
- Register ActiveLanesVreg =
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
- Register DstVreg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
- BuildMI(BB, MI, DL, TII->get(AMDGPU::V_CVT_F32_I32_e64), ActiveLanesVreg)
+ /// for FPop: #activebits: int, src: float.
+ /// convert int to float, and then mul. there is only V_MUL_F32, so
copy
+ /// to vgpr.
+ ///
/home/aalokdes/dockerx/work/llvm-trunk/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
+ /// ig: 1(01) -> negation, 2(10) -> abs, 3(11) -> abs and neg
+ // V_CVT_F32_I32_e64
+ // get #active lanes in vgpr
+ Register ActiveLanesVreg =
+ MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ Register DstVreg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ BuildMI(BB, MI, DL, TII->get(AMDGPU::V_CVT_F32_I32_e64),
+ ActiveLanesVreg)
// .addReg(SrcReg)
.addReg(NewAccumulator->getOperand(0).getReg())
- .addImm(0) // clamp
+ .addImm(0) // clamp
.addImm(0); // output-modifier
- // Multiply numactivelanes * src
- // Take negation of input for SUB reduction
- unsigned srcMod = Opc == AMDGPU::V_SUB_F32_e64 ? 1 : 0; // check this to
make sure i am taking negation
- BuildMI(BB, MI, DL, TII->get(AMDGPU::V_MUL_F32_e64), DstVreg)
+ // Multiply numactivelanes * src
+ // Take negation of input for SUB reduction
+ unsigned srcMod =
+ Opc == AMDGPU::V_SUB_F32_e64
+ ? 1
+ : 0; // check this to make sure i am taking negation
+ BuildMI(BB, MI, DL, TII->get(AMDGPU::V_MUL_F32_e64), DstVreg)
.addImm(srcMod) // src0 modifier
.addReg(SrcReg)
.addImm(0) // src1 modifier
.addReg(ActiveLanesVreg)
- .addImm(0) // clamp
+ .addImm(0) // clamp
.addImm(0); // output-mod
- BuildMI(BB, MI, DL,
- TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
- .addReg(DstVreg);
+ BuildMI(BB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
+ .addReg(DstVreg);
}
}
RetBB = &BB;
``````````
</details>
https://github.com/llvm/llvm-project/pull/161815
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