llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-aarch64 Author: Sergei Barannikov (s-barannikov) <details> <summary>Changes</summary> These instructions can now be fully decoded automatically. --- Patch is 27.78 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/156364.diff 5 Files Affected: - (modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (+18-7) - (modified) llvm/lib/Target/AArch64/CMakeLists.txt (+1-2) - (modified) llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (+27-27) - (modified) llvm/lib/Target/AArch64/SMEInstrFormats.td (+55-1) - (modified) llvm/lib/Target/AArch64/SVEInstrFormats.td (+6-2) ``````````diff diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 8958ad129269c..78d683a4b4256 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1561,13 +1561,12 @@ def VectorIndexHOperand : AsmVectorIndex<0, 7>; def VectorIndexSOperand : AsmVectorIndex<0, 3>; def VectorIndexDOperand : AsmVectorIndex<0, 1>; -let OperandNamespace = "AArch64" in { - let OperandType = "OPERAND_IMPLICIT_IMM_0" in { - defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand, - [{ return ((uint64_t)Imm) == 0; }]>; - defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand, - [{ return ((uint32_t)Imm) == 0; }]>; - } +let OperandNamespace = "AArch64", OperandType = "OPERAND_IMPLICIT_IMM_0", + DecoderMethod = "DecodeZeroImm" in { + defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand, + [{ return ((uint64_t)Imm) == 0; }]>; + defm VectorIndex032b : VectorIndex<i32, VectorIndex0Operand, + [{ return ((uint32_t)Imm) == 0; }]>; } defm VectorIndex1 : VectorIndex<i64, VectorIndex1Operand, [{ return ((uint64_t)Imm) == 1; }]>; @@ -1620,6 +1619,7 @@ def sme_elm_idx0_0 : Operand<i32>, TImmLeaf<i32, [{ let PrintMethod = "printMatrixIndex"; let OperandNamespace = "AArch64"; let OperandType = "OPERAND_IMPLICIT_IMM_0"; + let DecoderMethod = "DecodeZeroImm"; } def sme_elm_idx0_1 : Operand<i32>, TImmLeaf<i32, [{ return ((uint32_t)Imm) <= 1; @@ -1683,6 +1683,7 @@ def uimm0s2range : Operand<i64>, ImmLeaf<i64, let ParserMatchClass = UImm0s2RangeOperand; let OperandNamespace = "AArch64"; let OperandType = "OPERAND_IMPLICIT_IMM_0"; + let DecoderMethod = "DecodeZeroImm"; } def uimm0s4range : Operand<i64>, ImmLeaf<i64, @@ -1691,6 +1692,7 @@ def uimm0s4range : Operand<i64>, ImmLeaf<i64, let ParserMatchClass = UImm0s4RangeOperand; let OperandNamespace = "AArch64"; let OperandType = "OPERAND_IMPLICIT_IMM_0"; + let DecoderMethod = "DecodeZeroImm"; } def uimm1s2range : Operand<i64>, ImmLeaf<i64, @@ -8220,18 +8222,23 @@ multiclass SMov { // streaming mode. let Predicates = [HasNEONandIsStreamingSafe] in { def vi8to32_idx0 : SIMDSMov<0, ".b", GPR32, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b00001; } def vi8to64_idx0 : SIMDSMov<1, ".b", GPR64, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b00001; } def vi16to32_idx0 : SIMDSMov<0, ".h", GPR32, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b00010; } def vi16to64_idx0 : SIMDSMov<1, ".h", GPR64, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b00010; } def vi32to64_idx0 : SIMDSMov<1, ".s", GPR64, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b00100; } } @@ -8267,15 +8274,19 @@ multiclass UMov { // streaming mode. let Predicates = [HasNEONandIsStreamingSafe] in { def vi8_idx0 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b00001; } def vi16_idx0 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b00010; } def vi32_idx0 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b00100; } def vi64_idx0 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndex0> { + bits<0> idx; let Inst{20-16} = 0b01000; } def : SIMDMovAlias<"mov", ".s", diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt index 79b56ea9cf850..803943fd57c4d 100644 --- a/llvm/lib/Target/AArch64/CMakeLists.txt +++ b/llvm/lib/Target/AArch64/CMakeLists.txt @@ -7,8 +7,7 @@ tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer) tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1) tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv) tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel) -tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler - -ignore-non-decodable-operands) +tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel) tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel) tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 8c1e9f61693fb..647a6a3d76ef8 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -130,6 +130,18 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, return Success; } +static DecodeStatus DecodeMPRRegisterClass(MCInst &Inst, + const MCDisassembler *Decoder) { + Inst.addOperand(MCOperand::createReg(AArch64::ZA)); + return Success; +} + +static DecodeStatus DecodeZTRRegisterClass(MCInst &Inst, + const MCDisassembler *Decoder) { + Inst.addOperand(MCOperand::createReg(AArch64::ZT0)); + return Success; +} + static const MCPhysReg MatrixZATileDecoderTable[5][16] = { {AArch64::ZAB0}, {AArch64::ZAH0, AArch64::ZAH1}, @@ -141,10 +153,19 @@ static const MCPhysReg MatrixZATileDecoderTable[5][16] = { AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13, AArch64::ZAQ14, AArch64::ZAQ15}}; +template <unsigned NumBitsForTile> +static DecodeStatus DecodeMatrixTile(MCInst &Inst, + const MCDisassembler *Decoder) { + static_assert(NumBitsForTile == 0); + Inst.addOperand(MCOperand::createReg(AArch64::ZAB0)); + return Success; +} + template <unsigned NumBitsForTile> static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder) { + static_assert(NumBitsForTile != 0); unsigned LastReg = (1 << NumBitsForTile) - 1; if (RegNo > LastReg) return Fail; @@ -1422,6 +1443,11 @@ DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, return Success; } +static DecodeStatus DecodeZeroImm(MCInst &Inst, const MCDisassembler *Decoder) { + Inst.addOperand(MCOperand::createImm(0)); + return Success; +} + template <int Bits> static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, const MCDisassembler *Decoder) { @@ -1570,6 +1596,7 @@ DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr, unsigned RnBits = fieldFromInstruction(Bits, 5, 5); unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4); + DecodeMPRRegisterClass(Inst, Decoder); DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_12_15RegClassID, 0, 4>( Inst, RvBits, Addr, Decoder); Inst.addOperand(MCOperand::createImm(Imm4Bits)); @@ -1613,33 +1640,6 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, for (const auto *Table : Tables) { DecodeStatus Result = decodeInstruction(Table, MI, Insn, Address, this, STI); - - const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); - - // For Scalable Matrix Extension (SME) instructions that have an implicit - // operand for the accumulator (ZA) or implicit immediate zero which isn't - // encoded, manually insert operand. - for (unsigned i = 0; i < Desc.getNumOperands(); i++) { - if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) { - switch (Desc.operands()[i].RegClass) { - default: - break; - case AArch64::MPRRegClassID: - MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA)); - break; - case AArch64::MPR8RegClassID: - MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0)); - break; - case AArch64::ZTRRegClassID: - MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0)); - break; - } - } else if (Desc.operands()[i].OperandType == - AArch64::OPERAND_IMPLICIT_IMM_0) { - MI.insert(MI.begin() + i, MCOperand::createImm(0)); - } - } - if (Result != MCDisassembler::Fail) return Result; } diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 40ec371fe79d3..d21c90e47439f 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -894,6 +894,7 @@ multiclass sme_mem_ld_v_ss<string mnemonic, bit is_col> { def _B : sme_mem_ld_ss_inst<0b0, 0b00, mnemonic # "b", !if(is_col, TileVectorOpV8, TileVectorOpH8), is_col, sme_elm_idx0_15, GPR64shifted8> { + bits<0> ZAt; bits<4> imm; let Inst{3-0} = imm; } @@ -925,6 +926,7 @@ multiclass sme_mem_ld_v_ss<string mnemonic, bit is_col> { !if(is_col, TileVectorOpV128, TileVectorOpH128), is_col, sme_elm_idx0_0, GPR64shifted128> { bits<4> ZAt; + bits<0> imm; let Inst{3-0} = ZAt; } @@ -1032,6 +1034,7 @@ multiclass sme_mem_st_v_ss<string mnemonic, bit is_col> { def _B : sme_mem_st_ss_inst<0b0, 0b00, mnemonic # "b", !if(is_col, TileVectorOpV8, TileVectorOpH8), is_col, sme_elm_idx0_15, GPR64shifted8> { + bits<0> ZAt; bits<4> imm; let Inst{3-0} = imm; } @@ -1063,6 +1066,7 @@ multiclass sme_mem_st_v_ss<string mnemonic, bit is_col> { !if(is_col, TileVectorOpV128, TileVectorOpH128), is_col, sme_elm_idx0_0, GPR64shifted128> { bits<4> ZAt; + bits<0> imm; let Inst{3-0} = ZAt; } @@ -1232,6 +1236,7 @@ multiclass sme_vector_v_to_tile<string mnemonic, bit is_col> { TileVectorOpH8), is_col, sme_elm_idx0_15, ZPR8, mnemonic>, SMEPseudo2Instr<NAME # _B, 1> { + bits<0> ZAd; bits<4> imm; let Inst{3-0} = imm; } @@ -1417,6 +1422,7 @@ multiclass sme_tile_to_vector_v<string mnemonic, bit is_col> { def _B : sme_tile_to_vector_inst<0b0, 0b00, ZPR8, !if(is_col, TileVectorOpV8, TileVectorOpH8), is_col, sme_elm_idx0_15, mnemonic> { + bits<0> ZAn; bits<4> imm; let Inst{8-5} = imm; let mayLoad = 1; @@ -1452,6 +1458,7 @@ multiclass sme_tile_to_vector_v<string mnemonic, bit is_col> { TileVectorOpH128), is_col, sme_elm_idx0_0, mnemonic> { bits<4> ZAn; + bits<0> imm; let Inst{8-5} = ZAn; let mayLoad = 1; } @@ -1738,6 +1745,7 @@ class sme2_dot_mla_add_sub_array_vg24_single<bits<7> op, sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm), mnemonic,"\t$ZAd[$Rv, $imm3, " # !if(op{5}, "vgx4", "vgx2") # "], $Zn, $Zm", "", []> , Sched<[]> { + bits<0> ZAd; bits<4> Zm; bits<5> Zn; bits<2> Rv; @@ -1805,6 +1813,7 @@ class sme2_dot_mla_add_sub_array_vg2_multi<bits<7> op, sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, multi_vector_ty:$Zm), mnemonic, "\t$ZAd[$Rv, $imm3, vgx2], $Zn, $Zm", "", []>, Sched<[]>{ + bits<0> ZAd; bits<4> Zm; bits<4> Zn; bits<2> Rv; @@ -1845,6 +1854,7 @@ class sme2_dot_mla_add_sub_array_vg4_multi<bits<7> op, sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, multi_vector_ty:$Zm), mnemonic, "\t$ZAd[$Rv, $imm3, vgx4], $Zn, $Zm", "", []>, Sched<[]>{ + bits<0> ZAd; bits<3> Zm; bits<3> Zn; bits<2> Rv; @@ -1887,6 +1897,7 @@ class sme2_multivec_accum_add_sub<string mnemonic, bit sz, bit vg4, bits<3> op, (ins matrix_ty:$_ZAdn, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, vector_ty:$Zm), mnemonic, "\t$ZAdn[$Rv, $imm3, " # !if(vg4, "vgx4", "vgx2") # "], $Zm", "", []>, Sched<[]> { + bits<0> ZAdn; bits<2> Rv; bits<3> imm3; let Inst{31-23} = 0b110000011; @@ -2129,6 +2140,7 @@ class sme2_mla_long_array_index_base<bits<2> op0, bits<2> op, Operand index_ty, (ins MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, index_ty:$imm, multi_vector_ty:$Zn, ZPR4b16:$Zm, VectorIndexH32b_timm:$i3), mnemonic, "\t$ZAda[$Rv, $imm" # !if(!eq(vg_acronym, ""), "", ", " # vg_acronym) # "], $Zn, $Zm$i3", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; let Inst{31-24} = 0b11000001; @@ -2243,6 +2255,7 @@ class sme2_mla_long_array<bits<2>op0, bits<2> op, index_ty:$imm, first_vector_ty:$Zn, second_vector_ty:$Zm), mnemonic,"\t$ZAda[$Rv, $imm" # !if(!eq(vg_acronym, ""), "", ", " # vg_acronym) # "], $Zn, $Zm", "", []> , Sched<[]> { + bits<0> ZAda; bits<2> Rv; let Inst{31-24} = 0b11000001; let Inst{23-22} = op0; @@ -2789,6 +2802,7 @@ class sme2_multi_vec_array_vg2_index<bits<2> sz, bits<6> op, MatrixOperand matri multi_vector_ty:$Zn, vector_ty:$Zm, index_ty:$i), mnemonic, "\t$ZAda[$Rv, $imm3, vgx2], $Zn, $Zm$i", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<4> Zn; @@ -2887,6 +2901,7 @@ class sme2_multi_vec_array_vg2_index_64b<bits<2> op, multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexD32b_timm:$i1), mnemonic, "\t$ZAda[$Rv, $imm3, vgx2], $Zn, $Zm$i1", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<1> i1; @@ -2931,6 +2946,7 @@ class sme2_multi_vec_array_vg4_index<bit sz, bits<7> op, MatrixOperand matrix_ty multi_vector_ty:$Zn, vector_ty:$Zm, index_ty:$i), mnemonic, "\t$ZAda[$Rv, $imm3, vgx4], $Zn, $Zm$i", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<3> Zn; @@ -3018,6 +3034,7 @@ class sme2_multi_vec_array_vg4_index_64b<bits<3> op, multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexD32b_timm:$i1), mnemonic, "\t$ZAda[$Rv, $imm3, vgx4], $Zn, $Zm$i1", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<1> i1; @@ -3062,6 +3079,7 @@ class sme2_fp8_fmlal_vg24_index_za16<bits<2> sz, bit vg4, bits<3> op, multi_vector_ty:$Zn, ZPR4b8:$Zm, VectorIndexB32b_timm:$i), mnemonic, "\t$ZAda[$Rv, $imm2, " # !if(vg4, "vgx4", "vgx2") # "], $Zn, $Zm$i", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<4> i; @@ -3119,6 +3137,7 @@ class sme2_fp8_fmlal_index_za16<string mnemonic, bits<2> sz,bits<2> op> (ins MatrixOp16:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm3s2range:$imm3, ZPR8:$Zn, ZPR4b8:$Zm, VectorIndexB32b_timm:$i), mnemonic, "\t$ZAda[$Rv, $imm3], $Zn, $Zm$i", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<4> i; @@ -3155,6 +3174,7 @@ class sme2_mla_ll_array_index_32b<string mnemonic, bits<2> sz, bits<3> op> (ins MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm2s4range:$imm2, ZPR8:$Zn, ZPR4b8:$Zm, VectorIndexB32b_timm:$i), mnemonic, "\t$ZAda[$Rv, $imm2], $Zn, $Zm$i", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<4> i; @@ -3191,6 +3211,7 @@ class sme2_mla_ll_array_index_64b<string mnemonic, bits<2> op> (ins MatrixOp64:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm2s4range:$imm2, ZPR16:$Zn, ZPR4b16:$Zm, VectorIndexH32b_timm:$i), mnemonic, "\t$ZAda[$Rv, $imm2], $Zn, $Zm$i", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<3> i; @@ -3226,6 +3247,7 @@ class sme2_mla_ll_array_vg24_index_32b<bits<2> sz, bit vg4, bits<3> op, vector_ty:$Zn, ZPR4b8:$Zm, VectorIndexB32b_timm:$i), mnemonic, "\t$ZAda[$Rv, $imm, " # !if(vg4, "vgx4", "vgx2") # "], $Zn, $Zm$i", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<4> i; @@ -3287,6 +3309,7 @@ class sme2_mla_ll_array_vg24_index_64b<bit vg4, bits<2> op, vector_ty:$Zn, ZPR4b16:$Zm, VectorIndexH32b_timm:$i), mnemonic, "\t$ZAda[$Rv, $imm, " # !if(vg4, "vgx4", "vgx2") # "], $Zn, $Zm$i", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<3> i; @@ -3349,6 +3372,7 @@ class sme2_mla_ll_array_single<string mnemonic, bits<5> op, vector_ty:$Zn, zpr_ty:$Zm), mnemonic, "\t$ZAda[$Rv, $imm], $Zn, $Zm", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<5> Zn; @@ -3387,6 +3411,7 @@ class sme2_mla_ll_array_vg24_single<bits<6> op, MatrixOperand matrix_ty, vector_ty:$Zn, zpr_ty:$Zm), mnemonic, "\t$ZAda[$Rv, $imm, " # !if(op{4}, "vgx4", "vgx2") # "], $Zn, $Zm", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<5> Zn; @@ -3447,6 +3472,7 @@ class sme2_mla_ll_array_vg2_multi<bits<5> op, MatrixOperand matrix_ty, vector_ty:$Zn, vector_ty:$Zm), mnemonic, "\t$ZAda[$Rv, $imm, vgx2], $Zn, $Zm", "", []>, Sched<[]> { + bits<0> ZAda; bits<4> Zm; bits<2> Rv; bits<4> Zn; @@ -3492,6 +3518,7 @@ class sme2_mla_ll_array_vg4_multi<bits<5> op,MatrixOperand matrix_ty, vector_ty:$Zn, vector_ty:$Zm), mnemonic, "\t$ZAda[$Rv, $imm, vgx4], $Zn, $Zm", "", []>, Sched<[]> { + bits<0> ZAda; bits<3> Zm; bits<2> Rv; bits<3> Zn; @@ -3638,6 +3665,7 @@ class sme2_zero_zt<string mnemonic, bits<4> opc> : I<(outs ZTR:$ZT), (ins ), mnemonic, "\t\\{ $ZT \\}", "", []>, Sched<[]> { + bits<0> ZT; let Inst{31-4} = 0b1100000001001000000000000000; let Inst{3-0} = opc; } @@ -3660,6 +3688,7 @@ class sme2_spill_fill_vector<string mnemonic, bits<8> opc> !if(opc{7}, (ins ZTR:$ZTt, GPR64sp:$Rn), (ins GPR64sp:$Rn)), mnemonic, "\t$ZTt, [$Rn]", "", []>, Sched<[]> { + bits<0> ZTt; bits<5> Rn; let Inst{31-22} = 0b1110000100; let Inst{21-16} = opc{7-2}; @@ -3690,6 +3719,7 @@ class sme2_movt_zt_to_scalar<string mnemonic, bits<7> opc> : I<(outs GPR64:$Rt), (ins ZTR:$ZTt, uimm3s8:$imm3), mnemonic, "\t$Rt, $ZTt[$imm3]", "", []>, Sched<[]> { + bits<0> ZTt; bits<3> imm3; bits<5> Rt; let Inst{31-15} = 0b11000000010011000; @@ -3702,6 +3732,7 @@ class sme2_movt_scalar_to_zt<string mnemonic, bits<7> opc> : I<(outs ZTR:$ZTt), (ins uimm3s8:$imm3, GPR64:$Rt), mnemonic, "\t$ZTt[$imm3], $Rt", "", []>, Sched<[]> { + bits<0> ZTt; bits<3> imm3; bits<5> Rt; let Inst{31-15} = 0b11000000010011100; @@ -3715,6 +3746,7 @@ class sme2_movt_zt_to_zt<string mnemonic, bits<7> opc> : I<(outs ZTR:$ZTt), (ins sme_elm_idx0_3:$off2, ZPRAny:$Zt), mnemonic, "\t$ZTt[$off2, mul vl], $Zt", "", []>, Sched<[]> { + bits<0> ZTt; bits<5> Zt; bits<2> off2; let Inst{31-14} = 0b110000000100111100; @@ -3748,6 +3780,7 @@ class sme2_luti_vector_index<bits<2> sz, bits<7> opc, RegisterOperand vector_ty, (ins ZTR:$ZTt, ZPRAny:$Zn, index_ty:$i), mnemonic, "\t$Zd, $ZTt, $Zn$i", "", []>, Sched<[]> { + bits<0> ZTt; bits<5> Zn; bits<5> Zd; let Inst{31-19} = 0b1100000011001; @@ -3817,6 +3850,7 @@ class sme2_luti_vector_vg2_index<bits<2> sz, bits<6> opc, RegisterOperand vector (ins ZTR:$ZTt, ZPRAny:$Zn, index_ty:$i), mnemonic, "\t$Zd, $ZTt, $Zn$i", "", []>, Sched<[]> { + bits<0> ZTt; bits<5> Zn; bits<4> Zd; let Inst{31-19} = 0b1100000010001; @@ -3862,6 +3896,7 @@ class sme2_luti_vector_vg4_index<bits<2> sz, bits<5>opc, RegisterOperand vector_ (ins ZTR:$ZTt, ZPRAny:$Zn, index_ty:$i), mnemonic, "\t$Zd, $ZTt, $Zn$i", "", []>, Sched<[]> { + bits<0> ZTt; bits<5> Zn; bits<3> Zd; let Inst{31-19} = 0b1100000010001; @@ -3944,6 +3979,7 @@ multiclass sme2_mova_vec_to_tile_vg2_multi_base<bit v, string mnemonic, SDPatter TileVectorOpH8), uimm3s2range, ZZ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/156364 _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
