================
@@ -5248,49 +5248,94 @@
AArch64TargetLowering::LowerLOOP_DEPENDENCE_MASK(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
uint64_t EltSize = Op.getConstantOperandVal(2);
- EVT VT = Op.getValueType();
+ EVT FullVT = Op.getValueType();
+ unsigned NumElements = FullVT.getVectorMinNumElements();
+ unsigned NumSplits = 0;
+ EVT EltVT;
switch (EltSize) {
case 1:
- if (VT != MVT::v16i8 && VT != MVT::nxv16i1)
- return SDValue();
+ EltVT = MVT::i8;
break;
case 2:
- if (VT != MVT::v8i8 && VT != MVT::nxv8i1)
- return SDValue();
+ if (NumElements >= 16)
----------------
sdesmalen-arm wrote:
When the number of elements is smaller, not returning `SDValue()` results in
selectiondag failures, e.g.
```
define <vscale x 4 x i1> @whilewr_64_split(ptr %a, ptr %b) {
entry:
%0 = call <vscale x 4 x i1> @llvm.loop.dependence.war.mask.nxv4i1(ptr %a, ptr
%b, i64 1)
ret <vscale x 4 x i1> %0
}
```
There seems to be missing test-coverage for that.
https://github.com/llvm/llvm-project/pull/153187
_______________________________________________
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
