================
@@ -86,6 +83,13 @@ bool
AArch64PostCoalescer::runOnMachineFunction(MachineFunction &MF) {
Changed = true;
break;
}
+ case AArch64::EXT_ZZZI:
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg1 = MI.getOperand(1).getReg();
+ if (SrcReg1 != DstReg) {
+ MRI->setRegAllocationHint(DstReg, 0, SrcReg1);
+ }
+ break;
----------------
gbossu wrote:
Note that this commit is really just a WIP to show we can slightly improve
codegen with some hints. I'm not sure it should remain in that PR.
https://github.com/llvm/llvm-project/pull/152554
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