Author: Chris Jackson Date: 2025-07-22T12:14:15+01:00 New Revision: c1f13913c8d0218c9f768716d8c1fc1f36bf2d51
URL: https://github.com/llvm/llvm-project/commit/c1f13913c8d0218c9f768716d8c1fc1f36bf2d51 DIFF: https://github.com/llvm/llvm-project/commit/c1f13913c8d0218c9f768716d8c1fc1f36bf2d51.diff LOG: Revert "[AMDGPU] Recognise bitmask operations as srcmods on integer types (#1…" This reverts commit c51b48be4785f104f3aff2ba4a839a5f54778c5b. Added: Modified: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll llvm/test/CodeGen/AMDGPU/saddsat.ll llvm/test/CodeGen/AMDGPU/ssubsat.ll Removed: llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll ################################################################################ diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index fe0e7eb279486..00c7f0eb6e9f1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -3059,38 +3059,6 @@ bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src, Src = Src.getOperand(0); } - // Convert various sign-bit masks to src mods. Currently disabled for 16-bit - // types as the codegen replaces the operand without adding a srcmod. - // This is intentionally finding the cases where we are performing float neg - // and abs on int types, the goal is not to obtain two's complement neg or - // abs. - // TODO: Add 16-bit support. - unsigned Opc = Src->getOpcode(); - EVT VT = Src.getValueType(); - if ((Opc != ISD::AND && Opc != ISD::OR && Opc != ISD::XOR) || - (VT != MVT::i32 && VT != MVT::v2i32 && VT != MVT::i64)) - return true; - - ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Src->getOperand(1)); - if (!CRHS) - return true; - - // Recognise (xor a, 0x80000000) as NEG SrcMod. - // Recognise (and a, 0x7fffffff) as ABS SrcMod. - // Recognise (or a, 0x80000000) as NEG+ABS SrcModifiers. - if (Opc == ISD::XOR && CRHS->getAPIntValue().isSignMask()) { - Mods |= SISrcMods::NEG; - Src = Src.getOperand(0); - } else if (Opc == ISD::AND && AllowAbs && - CRHS->getAPIntValue().isMaxSignedValue()) { - Mods |= SISrcMods::ABS; - Src = Src.getOperand(0); - } else if (Opc == ISD::OR && AllowAbs && CRHS->getAPIntValue().isSignMask()) { - Mods |= SISrcMods::ABS; - Mods |= SISrcMods::NEG; - Src = Src.getOperand(0); - } - return true; } diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll index 5674ae328406d..1b092b283290a 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll @@ -349,24 +349,29 @@ define i32 @select_fneg_xor_select_i32(i1 %cond0, i1 %cond1, i32 %arg0, i32 %arg ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_and_b32_e32 v0, 1, v0 -; GCN-NEXT: v_and_b32_e32 v1, 1, v1 +; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, v3, vcc +; GCN-NEXT: v_and_b32_e32 v1, 1, v1 +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, -v0, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: select_fneg_xor_select_i32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX11-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 ; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, v3, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, -v0, vcc_lo +; GFX11-NEXT: v_xor_b32_e32 v2, 0x80000000, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] %fneg0 = xor i32 %arg0, -2147483648 %select0 = select i1 %cond0, i32 %arg1, i32 %fneg0 @@ -545,25 +550,31 @@ define i64 @select_fneg_xor_select_i64(i1 %cond0, i1 %cond1, i64 %arg0, i64 %arg ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_and_b32_e32 v0, 1, v0 -; GCN-NEXT: v_and_b32_e32 v1, 1, v1 +; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GCN-NEXT: v_and_b32_e32 v1, 1, v1 ; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc -; GCN-NEXT: v_cndmask_b32_e64 v2, -v3, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc +; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, v2, -v2, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: select_fneg_xor_select_i64: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_and_b32 v1, 1, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v2, -v3, v5, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, -v2, vcc_lo +; GFX11-NEXT: v_xor_b32_e32 v3, 0x80000000, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] %fneg0 = xor i64 %arg0, 9223372036854775808 %select0 = select i1 %cond0, i64 %arg1, i64 %fneg0 diff --git a/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll b/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll deleted file mode 100644 index b3c7ac80dd014..0000000000000 --- a/llvm/test/CodeGen/AMDGPU/integer-select-src-modifiers.ll +++ /dev/null @@ -1,1011 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s - -define i32 @fneg_select_i32_1(i32 %cond, i32 %a, i32 %b) { -; GCN-LABEL: fneg_select_i32_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_select_i32_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -v1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i32 %a, u0x80000000 - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %neg.a, i32 %b - ret i32 %select -} - -define i32 @fneg_select_i32_2(i32 %cond, i32 %a, i32 %b) { -; GCN-LABEL: fneg_select_i32_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, -v1, v2, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_select_i32_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, -v1, v2, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i32 %a, u0x80000000 - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %b, i32 %neg.a - ret i32 %select -} - -define i32 @fneg_select_i32_both(i32 %cond, i32 %a, i32 %b) { -; GCN-LABEL: fneg_select_i32_both: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, -v1, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_select_i32_both: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, -v1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i32 %a, u0x80000000 - %neg.b = xor i32 %b, u0x80000000 - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %neg.a, i32 %neg.b - ret i32 %select -} - -define i32 @fneg_1_fabs_2_select_i32(i32 %cond, i32 %a, i32 %b) { -; GCN-LABEL: fneg_1_fabs_2_select_i32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, |v1|, -v1, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_1_fabs_2_select_i32: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, |v1|, -v1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i32 %a, u0x80000000 - %abs.b = and i32 %a, u0x7fffffff - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %neg.a, i32 %abs.b - ret i32 %select -} - -define i32 @s_fneg_select_i32_1(i32 inreg %cond, i32 inreg %a, i32 inreg %b) { -; GCN-LABEL: s_fneg_select_i32_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_xor_b32 s4, s17, 0x80000000 -; GCN-NEXT: s_cmp_eq_u32 s16, 0 -; GCN-NEXT: s_cselect_b32 s4, s4, s18 -; GCN-NEXT: v_mov_b32_e32 v0, s4 -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_select_i32_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_xor_b32 s1, s1, 0x80000000 -; GFX11-NEXT: s_cmp_eq_u32 s0, 0 -; GFX11-NEXT: s_cselect_b32 s0, s1, s2 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_mov_b32_e32 v0, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i32 %a, u0x80000000 - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %neg.a, i32 %b - ret i32 %select -} - -define i32 @s_fneg_1_fabs_2_select_i32(i32 inreg %cond, i32 %a, i32 %b) { -; GCN-LABEL: s_fneg_1_fabs_2_select_i32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_cmp_eq_u32 s16, 0 -; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 -; GCN-NEXT: v_cndmask_b32_e64 v0, |v0|, -v0, s[4:5] -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_1_fabs_2_select_i32: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_cmp_eq_u32 s0, 0 -; GFX11-NEXT: s_cselect_b32 s0, -1, 0 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_cndmask_b32_e64 v0, |v0|, -v0, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i32 %a, u0x80000000 - %abs.b = and i32 %a, u0x7fffffff - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %neg.a, i32 %abs.b - ret i32 %select -} - -define <2 x i32> @fneg_select_v2i32_1(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) { -; GCN-LABEL: fneg_select_v2i32_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v4, -v2, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_select_v2i32_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, -v2, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000) - %cmp = icmp eq <2 x i32> %cond, zeroinitializer - %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b - ret <2 x i32> %select -} - -define <2 x i32> @fneg_select_v2i32_2(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) { -; GCN-LABEL: fneg_select_v2i32_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_select_v2i32_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, v4, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000) - %cmp = icmp eq <2 x i32> %cond, zeroinitializer - %select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a - ret <2 x i32> %select -} - -define i32 @fabs_select_i32_1(i32 %cond, i32 %a, i32 %b) { -; GCN-LABEL: fabs_select_i32_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fabs_select_i32_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, |v1|, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = and i32 %a, u0x7fffffff - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %neg.a, i32 %b - ret i32 %select -} - -define i32 @fabs_select_i32_2(i32 %cond, i32 %a, i32 %b) { -; GCN-LABEL: fabs_select_i32_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fabs_select_i32_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, |v1|, v2, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = and i32 %a, u0x7fffffff - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %b, i32 %neg.a - ret i32 %select -} - -define <2 x i32> @fneg_1_fabs_2_select_v2i32(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) { -; GCN-LABEL: fneg_1_fabs_2_select_v2i32: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, -v2, |v2|, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, |v3|, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_1_fabs_2_select_v2i32: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, -v2, |v2|, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, |v3|, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000) - %abs.b = and <2 x i32> %a, splat (i32 u0x7fffffff) - %cmp = icmp eq <2 x i32> %cond, zeroinitializer - %select = select <2 x i1> %cmp, <2 x i32> %abs.b, <2 x i32> %neg.a - ret <2 x i32> %select -} - -define i32 @fneg_fabs_select_i32_1(i32 %cond, i32 %a, i32 %b) { -; GCN-LABEL: fneg_fabs_select_i32_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, -|v1|, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_fabs_select_i32_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -|v1|, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or i32 %a, u0x80000000 - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %neg.a, i32 %b - ret i32 %select -} - -define i32 @fneg_fabs_select_i32_2(i32 %cond, i32 %a, i32 %b) { -; GCN-LABEL: fneg_fabs_select_i32_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, -|v1|, v2, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_fabs_select_i32_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, -|v1|, v2, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or i32 %a, u0x80000000 - %cmp = icmp eq i32 %cond, zeroinitializer - %select = select i1 %cmp, i32 %b, i32 %neg.a - ret i32 %select -} - -define <2 x i32> @fneg_fabs_select_v2i32_1(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) { -; GCN-LABEL: fneg_fabs_select_v2i32_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v4, -|v2|, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_fabs_select_v2i32_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, -|v2|, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or <2 x i32> %a, splat (i32 u0x80000000) - %cmp = icmp eq <2 x i32> %cond, zeroinitializer - %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b - ret <2 x i32> %select -} - -define <2 x i32> @fneg_fabs_select_v2i32_2(<2 x i32> %cond, <2 x i32> %a, <2 x i32> %b) { -; GCN-LABEL: fneg_fabs_select_v2i32_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, -|v2|, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_fabs_select_v2i32_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, -|v2|, v4, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or <2 x i32> %a, splat (i32 u0x80000000) - %cmp = icmp eq <2 x i32> %cond, zeroinitializer - %select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a - ret <2 x i32> %select -} - - -define <2 x i32> @s_fneg_select_v2i32_1(<2 x i32> inreg %cond, <2 x i32> inreg %a, <2 x i32> inreg %b) { -; GCN-LABEL: s_fneg_select_v2i32_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_xor_b32 s4, s19, 0x80000000 -; GCN-NEXT: s_xor_b32 s5, s18, 0x80000000 -; GCN-NEXT: s_cmp_eq_u32 s16, 0 -; GCN-NEXT: s_cselect_b32 s5, s5, s20 -; GCN-NEXT: s_cmp_eq_u32 s17, 0 -; GCN-NEXT: s_cselect_b32 s4, s4, s21 -; GCN-NEXT: v_mov_b32_e32 v0, s5 -; GCN-NEXT: v_mov_b32_e32 v1, s4 -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_select_v2i32_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000 -; GFX11-NEXT: s_xor_b32 s2, s2, 0x80000000 -; GFX11-NEXT: s_cmp_eq_u32 s0, 0 -; GFX11-NEXT: s_cselect_b32 s0, s2, s16 -; GFX11-NEXT: s_cmp_eq_u32 s1, 0 -; GFX11-NEXT: s_cselect_b32 s1, s3, s17 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor <2 x i32> %a, splat (i32 u0x80000000) - %cmp = icmp eq <2 x i32> %cond, zeroinitializer - %select = select <2 x i1> %cmp, <2 x i32> %neg.a, <2 x i32> %b - ret <2 x i32> %select -} - -define <2 x i32> @s_fneg_fabs_select_v2i32_2(<2 x i32> inreg %cond, <2 x i32> inreg %a, <2 x i32> inreg %b) { -; GCN-LABEL: s_fneg_fabs_select_v2i32_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_bitset1_b32 s19, 31 -; GCN-NEXT: s_bitset1_b32 s18, 31 -; GCN-NEXT: s_cmp_eq_u32 s16, 0 -; GCN-NEXT: s_cselect_b32 s4, s20, s18 -; GCN-NEXT: s_cmp_eq_u32 s17, 0 -; GCN-NEXT: s_cselect_b32 s5, s21, s19 -; GCN-NEXT: v_mov_b32_e32 v0, s4 -; GCN-NEXT: v_mov_b32_e32 v1, s5 -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_fabs_select_v2i32_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_bitset1_b32 s3, 31 -; GFX11-NEXT: s_bitset1_b32 s2, 31 -; GFX11-NEXT: s_cmp_eq_u32 s0, 0 -; GFX11-NEXT: s_cselect_b32 s0, s16, s2 -; GFX11-NEXT: s_cmp_eq_u32 s1, 0 -; GFX11-NEXT: s_cselect_b32 s1, s17, s3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or <2 x i32> %a, splat (i32 u0x80000000) - %cmp = icmp eq <2 x i32> %cond, zeroinitializer - %select = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %neg.a - ret <2 x i32> %select -} - -define i64 @fneg_select_i64_1(i64 %cond, i64 %a, i64 %b) { -; GCN-LABEL: fneg_select_i64_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_select_i64_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v3, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i64 %a, u0x8000000000000000 - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %neg.a, i64 %b - ret i64 %select -} - -define i64 @fneg_select_i64_2(i64 %cond, i64 %a, i64 %b) { -; GCN-LABEL: fneg_select_i64_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_select_i64_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, -v3, v5, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i64 %a, u0x8000000000000000 - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %b, i64 %neg.a - ret i64 %select -} - -define i64 @fneg_1_fabs_2_select_i64(i64 %cond, i64 %a, i64 %b) { -; GCN-LABEL: fneg_1_fabs_2_select_i64: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, |v5|, -v3, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_1_fabs_2_select_i64: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, |v5|, -v3, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i64 %a, u0x8000000000000000 - %abs.b = and i64 %b, u0x7fffffffffffffff - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %neg.a, i64 %abs.b - ret i64 %select -} - -define i64 @fabs_select_i64_1(i64 %cond, i64 %a, i64 %b) { -; GCN-LABEL: fabs_select_i64_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fabs_select_i64_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, |v3|, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = and i64 %a, u0x7fffffffffffffff - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %neg.a, i64 %b - ret i64 %select -} - -define i64 @fabs_select_i64_2(i64 %cond, i64 %a, i64 %b) { -; GCN-LABEL: fabs_select_i64_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, |v3|, v5, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fabs_select_i64_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, |v3|, v5, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = and i64 %a, u0x7fffffffffffffff - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %b, i64 %neg.a - ret i64 %select -} - -define i64 @fneg_fabs_select_i64_1(i64 %cond, i64 %a, i64 %b) { -; GCN-LABEL: fneg_fabs_select_i64_1: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_fabs_select_i64_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -|v3|, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or i64 %a, u0x8000000000000000 - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %neg.a, i64 %b - ret i64 %select -} - -define i64 @fneg_fabs_select_i64_2(i64 %cond, i64 %a, i64 %b) { -; GCN-LABEL: fneg_fabs_select_i64_2: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc -; GCN-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: fneg_fabs_select_i64_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1] -; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, -|v3|, v5, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or i64 %a, u0x8000000000000000 - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %b, i64 %neg.a - ret i64 %select -} - -define i64 @s_fneg_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) { -; GFX7-LABEL: s_fneg_select_i64_1: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0 -; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000 -; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX7-NEXT: s_cselect_b32 s4, s18, s20 -; GFX7-NEXT: s_cselect_b32 s5, s6, s21 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: s_fneg_select_i64_1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000 -; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0 -; GFX9-NEXT: s_cselect_b32 s5, s18, s20 -; GFX9-NEXT: s_cselect_b32 s4, s4, s21 -; GFX9-NEXT: v_mov_b32_e32 v0, s5 -; GFX9-NEXT: v_mov_b32_e32 v1, s4 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_select_i64_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000 -; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0 -; GFX11-NEXT: s_cselect_b32 s0, s2, s16 -; GFX11-NEXT: s_cselect_b32 s1, s3, s17 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i64 %a, u0x8000000000000000 - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %neg.a, i64 %b - ret i64 %select -} - -define i64 @s_fneg_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) { -; GFX7-LABEL: s_fneg_select_i64_2: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0 -; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000 -; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX7-NEXT: s_cselect_b32 s4, s20, s18 -; GFX7-NEXT: s_cselect_b32 s5, s21, s6 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: s_fneg_select_i64_2: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000 -; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0 -; GFX9-NEXT: s_cselect_b32 s5, s20, s18 -; GFX9-NEXT: s_cselect_b32 s4, s21, s4 -; GFX9-NEXT: v_mov_b32_e32 v0, s5 -; GFX9-NEXT: v_mov_b32_e32 v1, s4 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_select_i64_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000 -; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0 -; GFX11-NEXT: s_cselect_b32 s0, s16, s2 -; GFX11-NEXT: s_cselect_b32 s1, s17, s3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i64 %a, u0x8000000000000000 - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %b, i64 %neg.a - ret i64 %select -} - -define i64 @s_fneg_1_fabs_2_select_i64(i64 inreg %cond, i64 inreg %a, i64 inreg %b) { -; GFX7-LABEL: s_fneg_1_fabs_2_select_i64: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0 -; GFX7-NEXT: s_xor_b32 s6, s19, 0x80000000 -; GFX7-NEXT: s_bitset0_b32 s21, 31 -; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX7-NEXT: s_cselect_b32 s4, s18, s20 -; GFX7-NEXT: s_cselect_b32 s5, s6, s21 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: s_fneg_1_fabs_2_select_i64: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_xor_b32 s4, s19, 0x80000000 -; GFX9-NEXT: s_bitset0_b32 s21, 31 -; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0 -; GFX9-NEXT: s_cselect_b32 s5, s18, s20 -; GFX9-NEXT: s_cselect_b32 s4, s4, s21 -; GFX9-NEXT: v_mov_b32_e32 v0, s5 -; GFX9-NEXT: v_mov_b32_e32 v1, s4 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_1_fabs_2_select_i64: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_xor_b32 s3, s3, 0x80000000 -; GFX11-NEXT: s_bitset0_b32 s17, 31 -; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0 -; GFX11-NEXT: s_cselect_b32 s0, s2, s16 -; GFX11-NEXT: s_cselect_b32 s1, s3, s17 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i64 %a, u0x8000000000000000 - %abs.b = and i64 %b, u0x7fffffffffffffff - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %neg.a, i64 %abs.b - ret i64 %select -} - -define i64 @s_fabs_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) { -; GFX7-LABEL: s_fabs_select_i64_1: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0 -; GFX7-NEXT: s_bitset0_b32 s19, 31 -; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX7-NEXT: s_cselect_b32 s4, s18, s20 -; GFX7-NEXT: s_cselect_b32 s5, s19, s21 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: s_fabs_select_i64_1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_bitset0_b32 s19, 31 -; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0 -; GFX9-NEXT: s_cselect_b32 s4, s18, s20 -; GFX9-NEXT: s_cselect_b32 s5, s19, s21 -; GFX9-NEXT: v_mov_b32_e32 v0, s4 -; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fabs_select_i64_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_bitset0_b32 s3, 31 -; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0 -; GFX11-NEXT: s_cselect_b32 s0, s2, s16 -; GFX11-NEXT: s_cselect_b32 s1, s3, s17 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = and i64 %a, u0x7fffffffffffffff - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %neg.a, i64 %b - ret i64 %select -} - -define i64 @s_fabs_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) { -; GFX7-LABEL: s_fabs_select_i64_2: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0 -; GFX7-NEXT: s_bitset0_b32 s19, 31 -; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX7-NEXT: s_cselect_b32 s4, s20, s18 -; GFX7-NEXT: s_cselect_b32 s5, s21, s19 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: s_fabs_select_i64_2: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_bitset0_b32 s19, 31 -; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0 -; GFX9-NEXT: s_cselect_b32 s4, s20, s18 -; GFX9-NEXT: s_cselect_b32 s5, s21, s19 -; GFX9-NEXT: v_mov_b32_e32 v0, s4 -; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fabs_select_i64_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_bitset0_b32 s3, 31 -; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0 -; GFX11-NEXT: s_cselect_b32 s0, s16, s2 -; GFX11-NEXT: s_cselect_b32 s1, s17, s3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = and i64 %a, u0x7fffffffffffffff - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %b, i64 %neg.a - ret i64 %select -} - -define i64 @s_fneg_fabs_select_i64_1(i64 inreg %cond, i64 inreg %a, i64 inreg %b) { -; GFX7-LABEL: s_fneg_fabs_select_i64_1: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0 -; GFX7-NEXT: s_bitset1_b32 s19, 31 -; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX7-NEXT: s_cselect_b32 s4, s18, s20 -; GFX7-NEXT: s_cselect_b32 s5, s19, s21 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: s_fneg_fabs_select_i64_1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_bitset1_b32 s19, 31 -; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0 -; GFX9-NEXT: s_cselect_b32 s4, s18, s20 -; GFX9-NEXT: s_cselect_b32 s5, s19, s21 -; GFX9-NEXT: v_mov_b32_e32 v0, s4 -; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_fabs_select_i64_1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_bitset1_b32 s3, 31 -; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0 -; GFX11-NEXT: s_cselect_b32 s0, s2, s16 -; GFX11-NEXT: s_cselect_b32 s1, s3, s17 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or i64 %a, u0x8000000000000000 - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %neg.a, i64 %b - ret i64 %select -} - -define i64 @s_fneg_fabs_select_i64_2(i64 inreg %cond, i64 inreg %a, i64 inreg %b) { -; GFX7-LABEL: s_fneg_fabs_select_i64_2: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u64_e64 s[4:5], s[16:17], 0 -; GFX7-NEXT: s_bitset1_b32 s19, 31 -; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX7-NEXT: s_cselect_b32 s4, s20, s18 -; GFX7-NEXT: s_cselect_b32 s5, s21, s19 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: s_fneg_fabs_select_i64_2: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_bitset1_b32 s19, 31 -; GFX9-NEXT: s_cmp_eq_u64 s[16:17], 0 -; GFX9-NEXT: s_cselect_b32 s4, s20, s18 -; GFX9-NEXT: s_cselect_b32 s5, s21, s19 -; GFX9-NEXT: v_mov_b32_e32 v0, s4 -; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: s_fneg_fabs_select_i64_2: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_bitset1_b32 s3, 31 -; GFX11-NEXT: s_cmp_eq_u64 s[0:1], 0 -; GFX11-NEXT: s_cselect_b32 s0, s16, s2 -; GFX11-NEXT: s_cselect_b32 s1, s17, s3 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_setpc_b64 s[30:31] - %neg.a = or i64 %a, u0x8000000000000000 - %cmp = icmp eq i64 %cond, zeroinitializer - %select = select i1 %cmp, i64 %b, i64 %neg.a - ret i64 %select -} - -define i16 @fneg_select_i16_1(i16 %cond, i16 %a, i16 %b) { -; GFX7-LABEL: fneg_select_i16_1: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fneg_select_i16_1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 -; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-TRUE16-LABEL: fneg_select_i16_1: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-FAKE16-LABEL: fneg_select_i16_1: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i16 %a, u0x8000 - %cmp = icmp eq i16 %cond, zeroinitializer - %select = select i1 %cmp, i16 %neg.a, i16 %b - ret i16 %select -} - -define i16 @fneg_select_i16_2(i16 %cond, i16 %a, i16 %b) { -; GFX7-LABEL: fneg_select_i16_2: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fneg_select_i16_2: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 -; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-TRUE16-LABEL: fneg_select_i16_2: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v2.l, vcc_lo -; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-FAKE16-LABEL: fneg_select_i16_2: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i16 %a, u0x8000 - %cmp = icmp eq i16 %cond, zeroinitializer - %select = select i1 %cmp, i16 %b, i16 %neg.a - ret i16 %select -} - -define i16 @fneg_select_i16_both(i16 %cond, i16 %a, i16 %b) { -; GFX7-LABEL: fneg_select_i16_both: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc -; GFX7-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fneg_select_i16_both: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc -; GFX9-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-TRUE16-LABEL: fneg_select_i16_both: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l -; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-FAKE16-LABEL: fneg_select_i16_both: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 -; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i16 %a, u0x8000 - %neg.b = xor i16 %b, u0x8000 - %cmp = icmp eq i16 %cond, zeroinitializer - %select = select i1 %cmp, i16 %neg.a, i16 %neg.b - ret i16 %select -} - -define i16 @fneg_1_fabs_2_select_i16(i16 %cond, i16 %a, i16 %b) { -; GFX7-LABEL: fneg_1_fabs_2_select_i16: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7-NEXT: v_xor_b32_e32 v2, 0xffff8000, v1 -; GFX7-NEXT: v_and_b32_e32 v1, 0x7fff, v1 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fneg_1_fabs_2_select_i16: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v2, 0xffff8000, v1 -; GFX9-NEXT: v_and_b32_e32 v1, 0x7fff, v1 -; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-TRUE16-LABEL: fneg_1_fabs_2_select_i16: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v1.l -; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l -; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.h, vcc_lo -; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-FAKE16-LABEL: fneg_1_fabs_2_select_i16: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: v_xor_b32_e32 v2, 0xffff8000, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1 -; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] - %neg.a = xor i16 %a, u0x8000 - %abs.b = and i16 %a, u0x7fff - %cmp = icmp eq i16 %cond, zeroinitializer - %select = select i1 %cmp, i16 %neg.a, i16 %abs.b - ret i16 %select -} diff --git a/llvm/test/CodeGen/AMDGPU/saddsat.ll b/llvm/test/CodeGen/AMDGPU/saddsat.ll index c52f7a4ac720a..4e27cf20d3c98 100644 --- a/llvm/test/CodeGen/AMDGPU/saddsat.ll +++ b/llvm/test/CodeGen/AMDGPU/saddsat.ll @@ -124,8 +124,9 @@ define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) { ; GFX6-NEXT: v_add_i32_e64 v1, s[4:5], v0, v1 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v1 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_saddsat_i32: @@ -135,8 +136,9 @@ define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) { ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v0, v1 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v1 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_saddsat_i32: @@ -381,14 +383,16 @@ define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { ; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v0, v2 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -v0, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v1, v3 ; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, -v1, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_saddsat_v2i32: @@ -398,14 +402,16 @@ define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v0, v2 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -v0, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v1, v3 ; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, -v1, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_saddsat_v2i32: @@ -436,7 +442,8 @@ define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) { ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v5 ; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc +; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_saddsat_i64: @@ -449,7 +456,8 @@ define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) { ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v5 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc +; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_saddsat_i64: @@ -462,7 +470,8 @@ define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) { ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v5 ; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc +; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_i64: @@ -471,11 +480,12 @@ define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) { ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2 ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[2:3] +; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] -; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v5 +; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v6 ; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_saddsat_i64: @@ -484,11 +494,11 @@ define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) { ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2 ; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v3, vcc_lo ; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3] +; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] -; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v5 +; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v6 ; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc_lo +; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_cndmask_b32 v1, v5, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs) ret i64 %result diff --git a/llvm/test/CodeGen/AMDGPU/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/ssubsat.ll index 09c0e775f783d..40d80f5e83e36 100644 --- a/llvm/test/CodeGen/AMDGPU/ssubsat.ll +++ b/llvm/test/CodeGen/AMDGPU/ssubsat.ll @@ -124,8 +124,9 @@ define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) { ; GFX6-NEXT: v_sub_i32_e64 v1, s[4:5], v0, v1 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v1 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_ssubsat_i32: @@ -135,8 +136,9 @@ define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) { ; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v0, v1 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v1 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_ssubsat_i32: @@ -381,14 +383,16 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { ; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v0, v2 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -v0, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, -v1, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_ssubsat_v2i32: @@ -398,14 +402,16 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { ; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v0, v2 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -v0, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v1, v3 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, -v1, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_ssubsat_v2i32: @@ -433,20 +439,23 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) { ; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v3 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v0, v3, -v0, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v4 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v3 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, -v1, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v2, v5 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2 ; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v3 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v2, v3, -v2, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_ssubsat_v3i32: @@ -456,20 +465,23 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) { ; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v0, v3 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v3, -v0, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v1, v4 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v3 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, -v1, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v2, v5 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v3 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, -v2, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_ssubsat_v3i32: @@ -499,26 +511,30 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { ; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v0, v4 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v4 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, -v0, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v1, v5 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v4 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, -v1, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc ; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v2, v6 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2 ; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v4 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, -v2, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v7 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3 ; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v4 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v3, v4, -v3, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_ssubsat_v4i32: @@ -528,26 +544,30 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { ; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v0, v4 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v4 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, -v0, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v1, v5 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v4 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, -v1, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc ; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v2, v6 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v4 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, -v2, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v3, v7 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v4 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, -v3, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_ssubsat_v4i32: @@ -579,50 +599,58 @@ define <8 x i32> @v_ssubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) { ; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v8 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v8 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v0, v8, -v0, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v1, v9 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v8 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v1, v8, -v1, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v2, v10 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2 ; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v8 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v2, v8, -v2, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v3, v11 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3 ; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v8 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v3, v8, -v3, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc ; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v4, v12 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4 ; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v8 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, -v4, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v13 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5 ; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v8 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v5, v8, -v5, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc ; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v14 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6 ; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v8 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, -v6, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v6, 0x80000000, v6 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v15 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7 ; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v8 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v7, v8, -v7, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v7, 0x80000000, v7 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_ssubsat_v8i32: @@ -632,50 +660,58 @@ define <8 x i32> @v_ssubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) { ; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v0, v8 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v8 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, -v0, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v1, v9 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v8 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v8, -v1, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v2, v10 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v8 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, -v2, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v3, v11 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v8 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v3, v8, -v3, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc ; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v4, v12 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4 ; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v8 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, -v4, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v5, v13 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5 ; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v8 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v5, v8, -v5, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc ; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v6, v14 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6 ; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v8 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, -v6, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v6, 0x80000000, v6 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc ; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v7, v15 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7 ; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v8 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v7, v8, -v7, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v7, 0x80000000, v7 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_ssubsat_v8i32: @@ -715,100 +751,116 @@ define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { ; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v0, v16 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v16 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v0, v16, -v0, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v1, v17 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v16 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v1, v16, -v1, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc ; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v2, v18 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2 ; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v16 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v2, v16, -v2, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc ; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v3, v19 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3 ; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v16 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v3, v16, -v3, s[4:5] -; GFX6-NEXT: buffer_load_dword v16, off, s[0:3], s32 -; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v4, v20 +; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v4, v20 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20 -; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v4 -; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v4, v17, -v4, s[4:5] +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4 +; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v16 +; GFX6-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc +; GFX6-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v5, v21 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v5 ; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v5, v17, -v5, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v6, v22 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v6 ; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v6, v17, -v6, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v6, 0x80000000, v6 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v6, v17, v6, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v7, v23 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v7 ; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v7, v17, -v7, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v7, 0x80000000, v7 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v8, v24 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v8 ; GFX6-NEXT: v_ashrrev_i32_e32 v8, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v8, v17, -v8, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v8, 0x80000000, v8 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v9, v25 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v9 ; GFX6-NEXT: v_ashrrev_i32_e32 v9, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v9, v17, -v9, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v9, 0x80000000, v9 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v10, v26 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v10 ; GFX6-NEXT: v_ashrrev_i32_e32 v10, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v10, v17, -v10, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v10, 0x80000000, v10 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v11, v27 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v11 ; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v11, v17, -v11, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v11, 0x80000000, v11 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v12, v28 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v12 ; GFX6-NEXT: v_ashrrev_i32_e32 v12, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v12, v17, -v12, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v12, 0x80000000, v12 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v13, v29 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v13 ; GFX6-NEXT: v_ashrrev_i32_e32 v13, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v13, v17, -v13, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v13, 0x80000000, v13 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc ; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v14, v30 ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v14 ; GFX6-NEXT: v_ashrrev_i32_e32 v14, 31, v17 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v14, v17, -v14, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v14, 0x80000000, v14 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc ; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 ; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v15, v16 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15 ; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v16 -; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX6-NEXT: v_cndmask_b32_e64 v15, v16, -v15, s[4:5] +; GFX6-NEXT: v_xor_b32_e32 v15, 0x80000000, v15 +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_ssubsat_v16i32: @@ -818,100 +870,116 @@ define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { ; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v0, v16 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v16 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, -v0, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v1, v17 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v16 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, -v1, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc ; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v2, v18 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v16 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, -v2, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc ; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v3, v19 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v16 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v3, v16, -v3, s[4:5] -; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 -; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v4, v20 +; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v4, v20 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20 -; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v4 -; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v4, v17, -v4, s[4:5] +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4 +; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v16 +; GFX8-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc +; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v5, v21 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v5 ; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v5, v17, -v5, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v6, v22 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v6 ; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v6, v17, -v6, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v6, 0x80000000, v6 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v6, v17, v6, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v7, v23 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v7 ; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v7, v17, -v7, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v7, 0x80000000, v7 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v8, v24 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v8 ; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v8, v17, -v8, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v8, 0x80000000, v8 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v9, v25 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v9 ; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v9, v17, -v9, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v9, 0x80000000, v9 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v10, v26 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v10 ; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v10, v17, -v10, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v10, 0x80000000, v10 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v11, v27 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v11 ; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v11, v17, -v11, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v11, 0x80000000, v11 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v12, v28 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v12 ; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v12, v17, -v12, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v12, 0x80000000, v12 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v13, v29 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v13 ; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v13, v17, -v13, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v13, 0x80000000, v13 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc ; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v14, v30 ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v14 ; GFX8-NEXT: v_ashrrev_i32_e32 v14, 31, v17 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v14, v17, -v14, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v14, 0x80000000, v14 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 ; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v15, v16 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15 ; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v16 -; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] -; GFX8-NEXT: v_cndmask_b32_e64 v15, v16, -v15, s[4:5] +; GFX8-NEXT: v_xor_b32_e32 v15, 0x80000000, v15 +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_ssubsat_v16i32: @@ -998,7 +1066,8 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v5 ; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc +; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_ssubsat_i64: @@ -1011,7 +1080,8 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v5 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc +; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_ssubsat_i64: @@ -1024,7 +1094,8 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v5 ; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc +; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_i64: @@ -1033,11 +1104,12 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 ; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[2:3] +; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] -; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v5 +; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v6 ; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_ssubsat_i64: @@ -1046,11 +1118,11 @@ define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { ; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 ; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, v1, v3, vcc_lo ; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[2:3] +; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] -; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v5 +; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v6 ; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc_lo +; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_cndmask_b32 v1, v5, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs) ret i64 %result _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
