================
@@ -392,6 +394,55 @@ void
AMDGPURegBankCombinerImpl::applyCanonicalizeZextShiftAmt(
MI.eraseFromParent();
}
+bool AMDGPURegBankCombinerImpl::lowerUniformBFX(MachineInstr &MI) const {
+ assert(MI.getOpcode() == TargetOpcode::G_UBFX ||
+ MI.getOpcode() == TargetOpcode::G_SBFX);
+ const bool Signed = (MI.getOpcode() == TargetOpcode::G_SBFX);
+
+ Register DstReg = MI.getOperand(0).getReg();
+ const RegisterBank *RB = RBI.getRegBank(DstReg, MRI, TRI);
+ assert(RB && "No RB?");
+ if (RB->getID() != AMDGPU::SGPRRegBankID)
+ return false;
+
+ Register SrcReg = MI.getOperand(1).getReg();
+ Register OffsetReg = MI.getOperand(2).getReg();
+ Register WidthReg = MI.getOperand(3).getReg();
+
+ const LLT S32 = LLT::scalar(32);
+ LLT Ty = MRI.getType(DstReg);
+
+ const unsigned Opc = Ty == S32
+ ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32)
+ : (Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64);
+
+ // Ensure the high bits are clear to insert the offset.
+ auto OffsetMask = B.buildConstant(S32, maskTrailingOnes<unsigned>(6));
+ auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
----------------
Pierre-vh wrote:
I'm doing it so the high bits are zero and the width doesn't get overwritten,
not really to sanitize the BFX's operand
Though I don't feel strongly about it, it's indeed UB if the value is out of
range so we don't really have to promise anything
Do you prefer if I remove the AND ?
https://github.com/llvm/llvm-project/pull/141589
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