https://github.com/aengelke updated
https://github.com/llvm/llvm-project/pull/142584
>From 4cbc231699c11444cff73ff28b88dc0f3835c752 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <enge...@in.tum.de>
Date: Wed, 4 Jun 2025 09:21:02 +0000
Subject: [PATCH 1/2] Move one check to beginning of function
Created using spr 1.3.5-bogner
---
llvm/lib/CodeGen/MachineBlockPlacement.cpp | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index e96f3f8193b09..2dbabfe345d5e 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -1483,6 +1483,11 @@ bool MachineBlockPlacement::hasBetterLayoutPredecessor(
if (SuccChain.UnscheduledPredecessors == 0)
return false;
+ // Compile-time optimization: runtime is quadratic in the number of
+ // predecessors. For such uncommon cases, exit early.
+ if (Succ->pred_size() > PredecessorLimit)
+ return false;
+
// There are two basic scenarios here:
// -------------------------------------
// Case 1: triangular shape CFG (if-then):
@@ -1603,11 +1608,6 @@ bool MachineBlockPlacement::hasBetterLayoutPredecessor(
BlockFrequency CandidateEdgeFreq = MBFI->getBlockFreq(BB) * RealSuccProb;
bool BadCFGConflict = false;
- // Compile-time optimization: runtime is quadratic in the number of
- // predecessors. For such uncommon cases, exit early.
- if (Succ->pred_size() > PredecessorLimit)
- return false;
-
for (MachineBasicBlock *Pred : Succ->predecessors()) {
BlockChain *PredChain = BlockToChain[Pred];
if (Pred == Succ || PredChain == &SuccChain ||
>From e90cfcb5740fc7297e05a876172ad8c25f596a33 Mon Sep 17 00:00:00 2001
From: Alexis Engelke <enge...@in.tum.de>
Date: Fri, 13 Jun 2025 15:43:00 +0000
Subject: [PATCH 2/2] Test new command line flag
Created using spr 1.3.5-bogner
---
llvm/test/CodeGen/RISCV/branch.ll | 49 +++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/branch.ll
b/llvm/test/CodeGen/RISCV/branch.ll
index 578080cd3a240..ed86ca8ca4dd1 100644
--- a/llvm/test/CodeGen/RISCV/branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs
-block-placement-predecessor-limit=10 < %s \
+; RUN: | FileCheck -check-prefix=RV32I-MBPLIMIT %s
define void @foo(i32 %a, ptr %b, i1 %c) nounwind {
; RV32I-LABEL: foo:
@@ -48,6 +50,53 @@ define void @foo(i32 %a, ptr %b, i1 %c) nounwind {
; RV32I-NEXT: lw zero, 0(a1)
; RV32I-NEXT: .LBB0_14: # %end
; RV32I-NEXT: ret
+;
+; RV32I-MBPLIMIT-LABEL: foo:
+; RV32I-MBPLIMIT: # %bb.0:
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bne a3, a0, .LBB0_2
+; RV32I-MBPLIMIT-NEXT: .LBB0_1: # %end
+; RV32I-MBPLIMIT-NEXT: ret
+; RV32I-MBPLIMIT-NEXT: .LBB0_2: # %test2
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bne a3, a0, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.3: # %test3
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: blt a3, a0, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.4: # %test4
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bge a3, a0, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.5: # %test5
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bltu a3, a0, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.6: # %test6
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bgeu a3, a0, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.7: # %test7
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: blt a0, a3, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.8: # %test8
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bge a0, a3, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.9: # %test9
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bltu a0, a3, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.10: # %test10
+; RV32I-MBPLIMIT-NEXT: lw a3, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bgeu a0, a3, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.11: # %test11
+; RV32I-MBPLIMIT-NEXT: lw zero, 0(a1)
+; RV32I-MBPLIMIT-NEXT: andi a2, a2, 1
+; RV32I-MBPLIMIT-NEXT: bnez a2, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.12: # %test12
+; RV32I-MBPLIMIT-NEXT: lw a0, 0(a1)
+; RV32I-MBPLIMIT-NEXT: bgez a0, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.13: # %test13
+; RV32I-MBPLIMIT-NEXT: lw a0, 0(a1)
+; RV32I-MBPLIMIT-NEXT: blez a0, .LBB0_1
+; RV32I-MBPLIMIT-NEXT: # %bb.14: # %test14
+; RV32I-MBPLIMIT-NEXT: lw zero, 0(a1)
+; RV32I-MBPLIMIT-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp eq i32 %val1, %a
br i1 %tst1, label %end, label %test2
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