================ @@ -2512,9 +2512,11 @@ bool RISCVTTIImpl::isProfitableToSinkOperands( RISCVTTIImpl::TTI::MemCmpExpansionOptions RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { TTI::MemCmpExpansionOptions Options; + // Here we assume that a core that has implemented unaligned vector access + // should also have implemented unaligned scalar access. ---------------- wangpc-pp wrote:
Hmmm, you are right that we only generate vle8.v here. I will change that. https://github.com/llvm/llvm-project/pull/114517 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits