llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: Stanislav Mekhanoshin (rampitec) <details> <summary>Changes</summary> --- Patch is 52.94 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/142910.diff 1 Files Affected: - (added) llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll (+1223) ``````````diff diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll new file mode 100644 index 0000000000000..243469d39cc11 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll @@ -0,0 +1,1223 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=CIVI,CI %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga < %s | FileCheck --check-prefixes=CIVI,VI %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s + +define amdgpu_kernel void @fneg_fabs_fadd_bf16(ptr addrspace(1) %out, bfloat %x, bfloat %y) { +; CI-LABEL: fneg_fabs_fadd_bf16: +; CI: ; %bb.0: +; CI-NEXT: s_load_dword s2, s[8:9], 0x2 +; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; CI-NEXT: s_add_i32 s12, s12, s17 +; CI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_and_b32 s3, s2, 0x7fff +; CI-NEXT: s_lshl_b32 s3, s3, 16 +; CI-NEXT: s_and_b32 s2, s2, 0xffff0000 +; CI-NEXT: v_mov_b32_e32 v0, s3 +; CI-NEXT: v_sub_f32_e32 v0, s2, v0 +; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; CI-NEXT: v_mov_b32_e32 v0, s0 +; CI-NEXT: v_mov_b32_e32 v1, s1 +; CI-NEXT: flat_store_short v[0:1], v2 +; CI-NEXT: s_endpgm +; +; VI-LABEL: fneg_fabs_fadd_bf16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dword s2, s[8:9], 0x8 +; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; VI-NEXT: s_add_i32 s12, s12, s17 +; VI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_and_b32 s3, s2, 0x7fff +; VI-NEXT: s_lshl_b32 s3, s3, 16 +; VI-NEXT: s_and_b32 s2, s2, 0xffff0000 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_sub_f32_e32 v0, s2, v0 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: flat_store_short v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: fneg_fabs_fadd_bf16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_and_b32 s3, s2, 0x7fff +; GFX9-NEXT: s_lshl_b32 s3, s3, 16 +; GFX9-NEXT: s_and_b32 s2, s2, 0xffff0000 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_sub_f32_e32 v1, s2, v1 +; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 +; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc +; GFX9-NEXT: global_store_short_d16_hi v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-TRUE16-LABEL: fneg_fabs_fadd_bf16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x8 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_mov_b32 s1, s0 +; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xffff0000 +; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0x7fff +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-TRUE16-NEXT: v_sub_f32_e64 v0, s0, s1 +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, v1, v2 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: global_store_d16_hi_b16 v3, v0, s[0:1] +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: fneg_fabs_fadd_bf16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x8 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0x7fff +; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff0000 +; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_sub_f32_e64 v0, s0, s1 +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, v1, v2 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: global_store_d16_hi_b16 v3, v0, s[0:1] +; GFX11-FAKE16-NEXT: s_endpgm + %fabs = call bfloat @llvm.fabs.bf16(bfloat %x) + %fsub = fsub bfloat -0.0, %fabs + %fadd = fadd bfloat %y, %fsub + store bfloat %fadd, ptr addrspace(1) %out, align 2 + ret void +} + +define amdgpu_kernel void @fneg_fabs_fmul_bf16(ptr addrspace(1) %out, bfloat %x, bfloat %y) { +; CI-LABEL: fneg_fabs_fmul_bf16: +; CI: ; %bb.0: +; CI-NEXT: s_load_dword s2, s[8:9], 0x2 +; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; CI-NEXT: s_add_i32 s12, s12, s17 +; CI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_and_b32 s3, s2, 0x7fff +; CI-NEXT: s_lshl_b32 s3, s3, 16 +; CI-NEXT: v_mul_f32_e64 v0, -1.0, s3 +; CI-NEXT: s_and_b32 s2, s2, 0xffff0000 +; CI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; CI-NEXT: v_mul_f32_e32 v0, s2, v0 +; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; CI-NEXT: v_mov_b32_e32 v0, s0 +; CI-NEXT: v_mov_b32_e32 v1, s1 +; CI-NEXT: flat_store_short v[0:1], v2 +; CI-NEXT: s_endpgm +; +; VI-LABEL: fneg_fabs_fmul_bf16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dword s2, s[8:9], 0x8 +; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; VI-NEXT: s_add_i32 s12, s12, s17 +; VI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_or_b32 s3, s2, 0x8000 +; VI-NEXT: s_lshl_b32 s3, s3, 16 +; VI-NEXT: s_and_b32 s2, s2, 0xffff0000 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_mul_f32_e32 v0, s2, v0 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: flat_store_short v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: fneg_fabs_fmul_bf16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_or_b32 s3, s2, 0x8000 +; GFX9-NEXT: s_lshl_b32 s3, s3, 16 +; GFX9-NEXT: s_and_b32 s2, s2, 0xffff0000 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_mul_f32_e32 v1, s2, v1 +; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 +; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc +; GFX9-NEXT: global_store_short_d16_hi v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-TRUE16-LABEL: fneg_fabs_fmul_bf16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x8 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_mov_b32 s1, s0 +; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xffff0000 +; GFX11-TRUE16-NEXT: s_bitset1_b32 s1, 15 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-TRUE16-NEXT: v_mul_f32_e64 v0, s0, s1 +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, v1, v2 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: global_store_d16_hi_b16 v3, v0, s[0:1] +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: fneg_fabs_fmul_bf16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x8 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_or_b32 s1, s0, 0x8000 +; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff0000 +; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_mul_f32_e64 v0, s0, s1 +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, v1, v2 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: global_store_d16_hi_b16 v3, v0, s[0:1] +; GFX11-FAKE16-NEXT: s_endpgm + %fabs = call bfloat @llvm.fabs.bf16(bfloat %x) + %fsub = fsub bfloat -0.0, %fabs + %fmul = fmul bfloat %y, %fsub + store bfloat %fmul, ptr addrspace(1) %out, align 2 + ret void +} + +; DAGCombiner will transform: +; (fabs (bf16 bitcast (i16 a))) => (bf16 bitcast (and (i16 a), 0x7FFFFFFF)) +; unless isFabsFree returns true +define amdgpu_kernel void @fneg_fabs_free_bf16(ptr addrspace(1) %out, i16 %in) { +; CI-LABEL: fneg_fabs_free_bf16: +; CI: ; %bb.0: +; CI-NEXT: s_load_dword s2, s[8:9], 0x2 +; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; CI-NEXT: s_add_i32 s12, s12, s17 +; CI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_and_b32 s2, s2, 0x7fff +; CI-NEXT: s_lshl_b32 s2, s2, 16 +; CI-NEXT: v_mul_f32_e64 v0, -1.0, s2 +; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; CI-NEXT: v_mov_b32_e32 v0, s0 +; CI-NEXT: v_mov_b32_e32 v1, s1 +; CI-NEXT: flat_store_short v[0:1], v2 +; CI-NEXT: s_endpgm +; +; VI-LABEL: fneg_fabs_free_bf16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dword s2, s[8:9], 0x8 +; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; VI-NEXT: s_add_i32 s12, s12, s17 +; VI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_bitset1_b32 s2, 15 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: flat_store_short v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: fneg_fabs_free_bf16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_bitset1_b32 s2, 15 +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: global_store_short v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-TRUE16-LABEL: fneg_fabs_free_bf16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8 +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: fneg_fabs_free_bf16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8 +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX11-FAKE16-NEXT: s_endpgm + %bc = bitcast i16 %in to bfloat + %fabs = call bfloat @llvm.fabs.bf16(bfloat %bc) + %fsub = fsub bfloat -0.0, %fabs + store bfloat %fsub, ptr addrspace(1) %out + ret void +} + +define amdgpu_kernel void @fneg_fabs_bf16(ptr addrspace(1) %out, bfloat %in) { +; CI-LABEL: fneg_fabs_bf16: +; CI: ; %bb.0: +; CI-NEXT: s_load_dword s2, s[8:9], 0x2 +; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; CI-NEXT: s_add_i32 s12, s12, s17 +; CI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_and_b32 s2, s2, 0x7fff +; CI-NEXT: s_lshl_b32 s2, s2, 16 +; CI-NEXT: v_mul_f32_e64 v0, -1.0, s2 +; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; CI-NEXT: v_mov_b32_e32 v0, s0 +; CI-NEXT: v_mov_b32_e32 v1, s1 +; CI-NEXT: flat_store_short v[0:1], v2 +; CI-NEXT: s_endpgm +; +; VI-LABEL: fneg_fabs_bf16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dword s2, s[8:9], 0x8 +; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; VI-NEXT: s_add_i32 s12, s12, s17 +; VI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_bitset1_b32 s2, 15 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: flat_store_short v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: fneg_fabs_bf16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_bitset1_b32 s2, 15 +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: global_store_short v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-TRUE16-LABEL: fneg_fabs_bf16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8 +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: fneg_fabs_bf16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8 +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX11-FAKE16-NEXT: s_endpgm + %fabs = call bfloat @llvm.fabs.bf16(bfloat %in) + %fsub = fsub bfloat -0.0, %fabs + store bfloat %fsub, ptr addrspace(1) %out, align 2 + ret void +} + +define amdgpu_kernel void @v_fneg_fabs_bf16(ptr addrspace(1) %out, ptr addrspace(1) %in) { +; CI-LABEL: v_fneg_fabs_bf16: +; CI: ; %bb.0: +; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; CI-NEXT: s_add_i32 s12, s12, s17 +; CI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_mov_b32_e32 v0, s2 +; CI-NEXT: v_mov_b32_e32 v1, s3 +; CI-NEXT: flat_load_ushort v2, v[0:1] +; CI-NEXT: v_mov_b32_e32 v0, s0 +; CI-NEXT: v_mov_b32_e32 v1, s1 +; CI-NEXT: s_waitcnt vmcnt(0) +; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; CI-NEXT: v_mul_f32_e64 v2, 1.0, |v2| +; CI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; CI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; CI-NEXT: flat_store_short v[0:1], v2 +; CI-NEXT: s_endpgm +; +; VI-LABEL: v_fneg_fabs_bf16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; VI-NEXT: s_add_i32 s12, s12, s17 +; VI-NEXT: s_mov_b32 flat_scratch_lo, s13 +; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: flat_load_ushort v2, v[0:1] +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_e32 v2, 0x8000, v2 +; VI-NEXT: flat_store_short v[0:1], v2 +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: v_fneg_fabs_bf16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_or_b32_e32 v1, 0x8000, v1 +; GFX9-NEXT: global_store_short v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX11-TRUE16-LABEL: v_fneg_fabs_bf16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3] +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, 0x8000, v0 +; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: v_fneg_fabs_bf16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, 0x8000, v1 +; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX11-FAKE16-NEXT: s_endpgm + %val = load bfloat, ptr addrspace(1) %in, align 2 + %fabs = call bfloat @llvm.fabs.bf16(bfloat %val) + %fsub = fsub bfloat -0.0, %fabs + store bfloat %fsub, ptr addrspace(1) %out, align 2 + ret void +} + +define amdgpu_kernel void @s_fneg_fabs_v2bf16_non_bc_src(ptr addrspace(1) %out, <2 x bfloat> %in) { +; CI-LABEL: s_fneg_fabs_v2bf16_non_bc_src: +; CI: ; %bb.0: +; CI-NEXT: s_load_dword s2, s[8:9], 0x2 +; ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/142910 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
