================
@@ -294,4 +294,13 @@ def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
// VIS3 instruction patterns.
let Predicates = [HasVIS3] in {
def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>;
+
+def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>;
+// Signed "MULXHI".
+// Based on the formula presented in OSA2011 ยง7.140, but with bitops to select
+// the values to be added.
+def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)),
+ (SUBrr (UMULXHI $lhs, $rhs),
+ (ADDrr (ANDrr (SRAXri $lhs, 63), $rhs),
+ (ANDrr (SRAXri $rhs, 63), $lhs)))>;
----------------
s-barannikov wrote:
Thanks for trying.
It probably needs more work at SparcTargetLowering for the expansion to be
optimal. Can you add a TODO near the pattern that reads something like
"Consider moving this expansion to DAG legalization phase"?
(For the record: I don't really understand the expansion and assume it is taken
from a proved source, like Sparc architecture manual.)
https://github.com/llvm/llvm-project/pull/135714
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