llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mc Author: Fangrui Song (MaskRay) <details> <summary>Changes</summary> now that llc supports `-M no-aliases` (along with llvm-mc and llvm-objdump). --- Patch is 20.70 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/134879.diff 27 Files Affected: - (modified) llvm/test/CodeGen/RISCV/add-before-shl.ll (+6-6) - (modified) llvm/test/CodeGen/RISCV/kcfi.ll (+2-2) - (modified) llvm/test/CodeGen/RISCV/patchable-function-entry.ll (+4-4) - (modified) llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll (+1-1) - (modified) llvm/test/MC/RISCV/rv32p-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/rv64p-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqciac-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcibi-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcibm-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcicli-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcicm-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqciint-csrs-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqciint-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqciio-aliases-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqciio-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcilb-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcili-li.s (+2-2) - (modified) llvm/test/MC/RISCV/xqcili-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcilia-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcilo-aliases-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcilo-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcisim-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xqcisync-valid.s (+1-1) - (modified) llvm/test/MC/RISCV/xrivosvisni-valid.s (+2-2) - (modified) llvm/test/MC/RISCV/xrivosvizip-valid.s (+2-2) ``````````diff diff --git a/llvm/test/CodeGen/RISCV/add-before-shl.ll b/llvm/test/CodeGen/RISCV/add-before-shl.ll index 5d4478f9d4b5f..b6ff3c9060af5 100644 --- a/llvm/test/CodeGen/RISCV/add-before-shl.ll +++ b/llvm/test/CodeGen/RISCV/add-before-shl.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -verify-machineinstrs --riscv-no-aliases < %s \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -M no-aliases < %s \ ; RUN: | FileCheck -check-prefixes=RV32I %s -; RUN: llc -mtriple=riscv64 -verify-machineinstrs --riscv-no-aliases < %s \ +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -M no-aliases < %s \ ; RUN: | FileCheck -check-prefixes=RV64I %s -; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs --riscv-no-aliases \ +; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs -M no-aliases \ ; RUN: < %s | FileCheck -check-prefixes=RV32C %s -; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \ +; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs -M no-aliases \ ; RUN: < %s | FileCheck -check-prefixes=RV64C %s -; RUN: llc -mtriple=riscv32 -mattr=+zca -verify-machineinstrs --riscv-no-aliases \ +; RUN: llc -mtriple=riscv32 -mattr=+zca -verify-machineinstrs -M no-aliases \ ; RUN: < %s | FileCheck -check-prefixes=RV32C %s -; RUN: llc -mtriple=riscv64 -mattr=+zca -verify-machineinstrs --riscv-no-aliases \ +; RUN: llc -mtriple=riscv64 -mattr=+zca -verify-machineinstrs -M no-aliases \ ; RUN: < %s | FileCheck -check-prefixes=RV64C %s ; These test that constant adds are not moved after shifts by DAGCombine, diff --git a/llvm/test/CodeGen/RISCV/kcfi.ll b/llvm/test/CodeGen/RISCV/kcfi.ll index 52be56fcbf55f..145ab5b4fa6e8 100644 --- a/llvm/test/CodeGen/RISCV/kcfi.ll +++ b/llvm/test/CodeGen/RISCV/kcfi.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -riscv-no-aliases < %s \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -M no-aliases < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -verify-machineinstrs -riscv-no-aliases < %s \ +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -M no-aliases < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 ; CHECK: .word 12345678 diff --git a/llvm/test/CodeGen/RISCV/patchable-function-entry.ll b/llvm/test/CodeGen/RISCV/patchable-function-entry.ll index 4eeb1bf313858..dc6521c9e4f7f 100644 --- a/llvm/test/CodeGen/RISCV/patchable-function-entry.ll +++ b/llvm/test/CodeGen/RISCV/patchable-function-entry.ll @@ -1,8 +1,8 @@ ;; Test the function attribute "patchable-function-entry". -; RUN: llc -mtriple=riscv32 --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,NORVC -; RUN: llc -mtriple=riscv64 --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,NORVC -; RUN: llc -mtriple=riscv32 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC -; RUN: llc -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC +; RUN: llc -mtriple=riscv32 -M no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,NORVC +; RUN: llc -mtriple=riscv64 -M no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,NORVC +; RUN: llc -mtriple=riscv32 -mattr=+c -M no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC +; RUN: llc -mtriple=riscv64 -mattr=+c -M no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC define void @f0() "patchable-function-entry"="0" { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll index 9ac2775d30668..b8305c193f83d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll +++ b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs --riscv-no-aliases < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -M no-aliases < %s | FileCheck %s target triple = "riscv64-unknown-unknown-elf" diff --git a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll index fb25d4e15e40e..cd896c9fa0f08 100644 --- a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll +++ b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v -verify-machineinstrs \ -; RUN: --riscv-no-aliases < %s | FileCheck %s +; RUN: -M no-aliases < %s | FileCheck %s target triple = "riscv64-unknown-unknown-elf" diff --git a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll index 853f937bbd230..588514ea82fdb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll +++ b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v -verify-machineinstrs \ -; RUN: --riscv-no-aliases < %s | FileCheck %s +; RUN: -M no-aliases < %s | FileCheck %s target triple = "riscv64-unknown-unknown-elf" diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s index 011de0c0d1579..e2e366593f9b9 100644 --- a/llvm/test/MC/RISCV/rv32p-valid.s +++ b/llvm/test/MC/RISCV/rv32p-valid.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-p -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-p -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \ # RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \ diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s index 48fa26aaaffe4..1ec5ee312e100 100644 --- a/llvm/test/MC/RISCV/rv64p-valid.s +++ b/llvm/test/MC/RISCV/rv64p-valid.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-p < %s \ # RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \ diff --git a/llvm/test/MC/RISCV/xqciac-valid.s b/llvm/test/MC/RISCV/xqciac-valid.s index c786d7c4ea51d..438c4cafe0dfe 100644 --- a/llvm/test/MC/RISCV/xqciac-valid.s +++ b/llvm/test/MC/RISCV/xqciac-valid.s @@ -1,5 +1,5 @@ # Xqciac - Qualcomm uC Load-Store Address Calculation Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqciac -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcibi-valid.s b/llvm/test/MC/RISCV/xqcibi-valid.s index 194f02f041771..63d35f3cafb80 100644 --- a/llvm/test/MC/RISCV/xqcibi-valid.s +++ b/llvm/test/MC/RISCV/xqcibi-valid.s @@ -1,5 +1,5 @@ # Xqcibi - Qualcomm uC Branch Immediate Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibi -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibi -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibi < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcibi -M no-aliases -d - \ diff --git a/llvm/test/MC/RISCV/xqcibm-valid.s b/llvm/test/MC/RISCV/xqcibm-valid.s index 70248ad00cb76..4e1db5db14332 100644 --- a/llvm/test/MC/RISCV/xqcibm-valid.s +++ b/llvm/test/MC/RISCV/xqcibm-valid.s @@ -1,5 +1,5 @@ # Xqcibm - Qualcomm uC Bit Manipulation Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcibm -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcicli-valid.s b/llvm/test/MC/RISCV/xqcicli-valid.s index 404bfdf7bce26..006151967bcf5 100644 --- a/llvm/test/MC/RISCV/xqcicli-valid.s +++ b/llvm/test/MC/RISCV/xqcicli-valid.s @@ -1,5 +1,5 @@ # Xqcicli - Qualcomm uC Conditional Load Immediate Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicli -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicli -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicli < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcicli -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcicm-valid.s b/llvm/test/MC/RISCV/xqcicm-valid.s index 7d0050b6dafa8..428ce3aa5f496 100644 --- a/llvm/test/MC/RISCV/xqcicm-valid.s +++ b/llvm/test/MC/RISCV/xqcicm-valid.s @@ -1,5 +1,5 @@ # Xqcicm - Qualcomm uC Conditional Move Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicm -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicm -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicm < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcicm -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqciint-csrs-valid.s b/llvm/test/MC/RISCV/xqciint-csrs-valid.s index 1e17974f5cb2c..e09dff39cce18 100644 --- a/llvm/test/MC/RISCV/xqciint-csrs-valid.s +++ b/llvm/test/MC/RISCV/xqciint-csrs-valid.s @@ -1,5 +1,5 @@ # Xqciint - Qualcomm uC Custom CSRs -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciint < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqciint -M no-aliases -d - \ diff --git a/llvm/test/MC/RISCV/xqciint-valid.s b/llvm/test/MC/RISCV/xqciint-valid.s index 1ea41956396d5..39812ab4d2ab4 100644 --- a/llvm/test/MC/RISCV/xqciint-valid.s +++ b/llvm/test/MC/RISCV/xqciint-valid.s @@ -1,5 +1,5 @@ # Xqciint - Qualcomm uC Interrupts extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciint < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqciint -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqciio-aliases-valid.s b/llvm/test/MC/RISCV/xqciio-aliases-valid.s index 6cebf2a0a05da..4738edb1f7ec7 100644 --- a/llvm/test/MC/RISCV/xqciio-aliases-valid.s +++ b/llvm/test/MC/RISCV/xqciio-aliases-valid.s @@ -1,5 +1,5 @@ # Xqciio - Qualcomm uC External Input Output extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciio < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqciio -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqciio-valid.s b/llvm/test/MC/RISCV/xqciio-valid.s index 912db65966de9..516f6219d0907 100644 --- a/llvm/test/MC/RISCV/xqciio-valid.s +++ b/llvm/test/MC/RISCV/xqciio-valid.s @@ -1,5 +1,5 @@ # Xqciio - Qualcomm uC External Input Output Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciio < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqciio -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcilb-valid.s b/llvm/test/MC/RISCV/xqcilb-valid.s index 1c722e3b3173e..2b871f085438f 100644 --- a/llvm/test/MC/RISCV/xqcilb-valid.s +++ b/llvm/test/MC/RISCV/xqcilb-valid.s @@ -1,5 +1,5 @@ # Xqcilb - Qualcomm uC Long Branch Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilb -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilb -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcilb -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcili-li.s b/llvm/test/MC/RISCV/xqcili-li.s index 47eefffe88026..7f684095cc02e 100644 --- a/llvm/test/MC/RISCV/xqcili-li.s +++ b/llvm/test/MC/RISCV/xqcili-li.s @@ -1,7 +1,7 @@ # Xqcili - Check aliases for li instruction -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -riscv-no-aliases \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -M no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \ +# RUN: llvm-mc %s -triple=riscv32 -M no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-INST-RISCV32 %s # CHECK-INST: qc.li a0, 2048 diff --git a/llvm/test/MC/RISCV/xqcili-valid.s b/llvm/test/MC/RISCV/xqcili-valid.s index 5e372c3dbd82f..c2f1bc2bd0c35 100644 --- a/llvm/test/MC/RISCV/xqcili-valid.s +++ b/llvm/test/MC/RISCV/xqcili-valid.s @@ -1,5 +1,5 @@ # Xqcili - Qualcomm uC Load Large Immediate Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcili < %s \ diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s index 49727d5d36239..03b20b04e3032 100644 --- a/llvm/test/MC/RISCV/xqcilia-valid.s +++ b/llvm/test/MC/RISCV/xqcilia-valid.s @@ -1,5 +1,5 @@ # Xqcilia - Qualcomm uC Large Immediate Arithmetic extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcilia -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcilo-aliases-valid.s b/llvm/test/MC/RISCV/xqcilo-aliases-valid.s index dddd76260b248..44f9bf7e894f7 100644 --- a/llvm/test/MC/RISCV/xqcilo-aliases-valid.s +++ b/llvm/test/MC/RISCV/xqcilo-aliases-valid.s @@ -1,5 +1,5 @@ # Xqcilo - Qualcomm uC Large Offset Load Store extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilo < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcilo -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcilo-valid.s b/llvm/test/MC/RISCV/xqcilo-valid.s index ce486e39313ab..f2ced4698c88a 100644 --- a/llvm/test/MC/RISCV/xqcilo-valid.s +++ b/llvm/test/MC/RISCV/xqcilo-valid.s @@ -1,5 +1,5 @@ # Xqcilo - Qualcomm uC Large Offset Load Store extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilo < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcilo -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcisim-valid.s b/llvm/test/MC/RISCV/xqcisim-valid.s index 668f279643c74..b5758f451ed6d 100644 --- a/llvm/test/MC/RISCV/xqcisim-valid.s +++ b/llvm/test/MC/RISCV/xqcisim-valid.s @@ -1,5 +1,5 @@ # Xqcisim - Simulation Hint Instructions -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcisim -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xqcisync-valid.s b/llvm/test/MC/RISCV/xqcisync-valid.s index 3eedf99247b22..4f0063a6a488c 100644 --- a/llvm/test/MC/RISCV/xqcisync-valid.s +++ b/llvm/test/MC/RISCV/xqcisync-valid.s @@ -1,5 +1,5 @@ # Xqcisync - Qualcomm uC Sync Delay Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \ # RUN: | llvm-objdump --mattr=+experimental-xqcisync -M no-aliases --no-print-imm-hex -d - \ diff --git a/llvm/test/MC/RISCV/xrivosvisni-valid.s b/llvm/test/MC/RISCV/xrivosvisni-valid.s index 3ef70001f3a9a..234545721eaf5 100644 --- a/llvm/test/MC/RISCV/xrivosvisni-valid.s +++ b/llvm/test/MC/RISCV/xrivosvisni-valid.s @@ -1,9 +1,9 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvisni -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvisni -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xrivosvisni < %s \ # RUN: | llvm-objdump --mattr=+experimental-xrivosvisni -M no-aliases --no-print-imm-hex -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvisni -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvisni -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xrivosvisni < %s \ # RUN: | llvm-objdump --mattr=+experimental-xrivosvisni -M no-aliases --no-print-imm-hex -d -r - \ diff --git a/llvm/test/MC/RISCV/xrivosvizip-valid.s b/llvm/test/MC/RISCV/xrivosvizip-valid.s index cab1ebb74f24f..55b51a05c023e 100644 --- a/llvm/test/MC/RISCV/xrivosvizip-valid.s +++ b/llvm/test/MC/RISCV/xrivosvizip-valid.s @@ -1,9 +1,9 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvizip -M no-aliases -show-encoding \ # RUN: | FileCheck -check-pre... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/134879 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
