https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/130086
Subregister defs are illegal in SSA. Surprisingly this enables folding
into subregister insert patterns in one test.
>From c7d08110c29c0c37c198fa02b953767eaf68a3be Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Thu, 6 Mar 2025 18:50:32 +0700
Subject: [PATCH] PeepholeOpt: Remove subreg def check for bitcast
Subregister defs are illegal in SSA. Surprisingly this enables folding
into subregister insert patterns in one test.
---
llvm/lib/CodeGen/PeepholeOptimizer.cpp | 9 ++++-----
llvm/test/CodeGen/X86/pr41619.ll | 2 --
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 4d0fd86eb216f..ec8e97f73546a 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1923,11 +1923,8 @@ ValueTrackerResult
ValueTracker::getNextSourceFromBitcast() {
// Bitcasts with more than one def are not supported.
if (Def->getDesc().getNumDefs() != 1)
return ValueTrackerResult();
- const MachineOperand DefOp = Def->getOperand(DefIdx);
- if (DefOp.getSubReg() != DefSubReg)
- // If we look for a different subreg, it means we want a subreg of the src.
- // Bails as we do not support composing subregs yet.
- return ValueTrackerResult();
+
+ assert(!Def->getOperand(DefIdx).getSubReg() && "no subregister defs in SSA");
unsigned SrcIdx = Def->getNumOperands();
for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
@@ -1950,6 +1947,8 @@ ValueTrackerResult
ValueTracker::getNextSourceFromBitcast() {
if (SrcIdx >= Def->getNumOperands())
return ValueTrackerResult();
+ const MachineOperand &DefOp = Def->getOperand(DefIdx);
+
// Stop when any user of the bitcast is a SUBREG_TO_REG, replacing with a
COPY
// will break the assumed guarantees for the upper bits.
for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg()))
{
diff --git a/llvm/test/CodeGen/X86/pr41619.ll b/llvm/test/CodeGen/X86/pr41619.ll
index 88dcd7798f0c3..6bca77d05e9a9 100644
--- a/llvm/test/CodeGen/X86/pr41619.ll
+++ b/llvm/test/CodeGen/X86/pr41619.ll
@@ -6,8 +6,6 @@ define void @foo(double %arg) {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %bb
; CHECK-NEXT: vmovq %xmm0, %rax
-; CHECK-NEXT: vmovd %eax, %xmm0
-; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: movl %eax, (%rax)
; CHECK-NEXT: movq $0, (%rax)
; CHECK-NEXT: retq
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
