llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: None (llvmbot) <details> <summary>Changes</summary> Backport 0d7ee520d3a9b8997adf8eaaa22b33db9659d94e Requested by: @<!-- -->topperc --- Full diff: https://github.com/llvm/llvm-project/pull/125953.diff 3 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-2) - (modified) llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll (+1) - (modified) llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll (+1) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 8d09e534b1858bc..8b5ee3e67ce637c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -16297,7 +16297,7 @@ static SDValue performVP_REVERSECombine(SDNode *N, SelectionDAG &DAG, SDValue Temp2 = DAG.getNode(ISD::MUL, DL, XLenVT, Temp1, DAG.getConstant(ElemWidthByte, DL, XLenVT)); SDValue Base = DAG.getNode(ISD::ADD, DL, XLenVT, VPLoad->getBasePtr(), Temp2); - SDValue Stride = DAG.getConstant(-ElemWidthByte, DL, XLenVT); + SDValue Stride = DAG.getSignedConstant(-ElemWidthByte, DL, XLenVT); MachineFunction &MF = DAG.getMachineFunction(); MachinePointerInfo PtrInfo(VPLoad->getAddressSpace()); @@ -16358,7 +16358,7 @@ static SDValue performVP_STORECombine(SDNode *N, SelectionDAG &DAG, DAG.getConstant(ElemWidthByte, DL, XLenVT)); SDValue Base = DAG.getNode(ISD::ADD, DL, XLenVT, VPStore->getBasePtr(), Temp2); - SDValue Stride = DAG.getConstant(-ElemWidthByte, DL, XLenVT); + SDValue Stride = DAG.getSignedConstant(-ElemWidthByte, DL, XLenVT); MachineFunction &MF = DAG.getMachineFunction(); MachinePointerInfo PtrInfo(VPStore->getAddressSpace()); diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll b/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll index 50e26bd14107002..24d8e56fa17febc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s define <vscale x 2 x float> @test_reverse_load_combiner(<vscale x 2 x float>* %ptr, i32 zeroext %evl) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll index 4896a1367935ac3..a2466c48b0ab7d9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s define void @test_store_reverse_combiner(<vscale x 2 x float> %val, <vscale x 2 x float>* %ptr, i32 zeroext %evl) { `````````` </details> https://github.com/llvm/llvm-project/pull/125953 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
