llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-backend-arm Author: Christudasan Devadasan (cdevadas) <details> <summary>Changes</summary> --- Patch is 63.84 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/125703.diff 56 Files Affected: - (modified) llvm/include/llvm/CodeGen/MachineScheduler.h (+18) - (modified) llvm/include/llvm/InitializePasses.h (+2-2) - (modified) llvm/include/llvm/Passes/CodeGenPassBuilder.h (+3-2) - (modified) llvm/include/llvm/Passes/MachinePassRegistry.def (+2-2) - (modified) llvm/lib/CodeGen/CodeGen.cpp (+2-2) - (modified) llvm/lib/CodeGen/MachineScheduler.cpp (+205-82) - (modified) llvm/lib/CodeGen/RegAllocBasic.cpp (+1-1) - (modified) llvm/lib/CodeGen/RegAllocGreedy.cpp (+1-1) - (modified) llvm/lib/Passes/PassBuilder.cpp (+1) - (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+2) - (modified) llvm/test/CodeGen/AArch64/a55-fuse-address.mir (+1) - (modified) llvm/test/CodeGen/AArch64/ampere1-sched-add.mir (+1) - (modified) llvm/test/CodeGen/AArch64/cluster-frame-index.mir (+1) - (modified) llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir (+6) - (modified) llvm/test/CodeGen/AArch64/dump-schedule-trace.mir (+17) - (modified) llvm/test/CodeGen/AArch64/force-enable-intervals.mir (+10) - (modified) llvm/test/CodeGen/AArch64/machine-scheduler.mir (+1) - (modified) llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir (+2) - (modified) llvm/test/CodeGen/AArch64/macro-fusion-last.mir (+2) - (modified) llvm/test/CodeGen/AArch64/misched-branch-targets.mir (+3) - (modified) llvm/test/CodeGen/AArch64/misched-bundle.mir (+1) - (modified) llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir (+8) - (modified) llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir (+7) - (modified) llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir (+2) - (modified) llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir (+1) - (modified) llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir (+3) - (modified) llvm/test/CodeGen/AArch64/misched-move-imm.mir (+1) - (modified) llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir (+1) - (modified) llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir (+10) - (modified) llvm/test/CodeGen/AArch64/sched-postidxalias.mir (+1) - (modified) llvm/test/CodeGen/AArch64/sched-print-cycle.mir (+6) - (modified) llvm/test/CodeGen/AArch64/scheduledag-constreg.mir (+1) - (modified) llvm/test/CodeGen/AArch64/sve-aliasing.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir (+2) - (modified) llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir (+4-2) - (modified) llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir (+2-1) - (modified) llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir (+2) - (modified) llvm/test/CodeGen/AMDGPU/schedule-barrier.mir (+1) - (modified) llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir (+1) - (modified) llvm/test/CodeGen/ARM/cortex-m7-wideops.mir (+1) - (modified) llvm/test/CodeGen/ARM/misched-branch-targets.mir (+2) - (modified) llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir (+1) - (modified) llvm/test/CodeGen/RISCV/misched-postra-direction.mir (+13) ``````````diff diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h index 4762494e6ccb77..e1f1a1efecc724 100644 --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -1385,6 +1385,24 @@ std::unique_ptr<ScheduleDAGMutation> createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI); +class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> { + const TargetMachine *TM; + +public: + MachineSchedulerPass(const TargetMachine *TM) : TM(TM) {} + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +class PostMachineSchedulerPass + : public PassInfoMixin<PostMachineSchedulerPass> { + const TargetMachine *TM; + +public: + PostMachineSchedulerPass(const TargetMachine *TM) : TM(TM) {} + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; } // end namespace llvm #endif // LLVM_CODEGEN_MACHINESCHEDULER_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 053f955d0df0a4..e492de62acfa48 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -209,7 +209,7 @@ void initializeMachinePipelinerPass(PassRegistry &); void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &); void initializeMachineRegionInfoPassPass(PassRegistry &); void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &); -void initializeMachineSchedulerPass(PassRegistry &); +void initializeMachineSchedulerLegacyPass(PassRegistry &); void initializeMachineSinkingPass(PassRegistry &); void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &); void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &); @@ -238,7 +238,7 @@ void initializePostDomPrinterWrapperPassPass(PassRegistry &); void initializePostDomViewerWrapperPassPass(PassRegistry &); void initializePostDominatorTreeWrapperPassPass(PassRegistry &); void initializePostInlineEntryExitInstrumenterPass(PassRegistry &); -void initializePostMachineSchedulerPass(PassRegistry &); +void initializePostMachineSchedulerLegacyPass(PassRegistry &); void initializePostRAHazardRecognizerPass(PassRegistry &); void initializePostRAMachineSinkingPass(PassRegistry &); void initializePostRASchedulerPass(PassRegistry &); diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 2e89875c06fa07..256c985b1390a9 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -50,6 +50,7 @@ #include "llvm/CodeGen/MachineLICM.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachinePassManager.h" +#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/MachineVerifier.h" #include "llvm/CodeGen/OptimizePHIs.h" #include "llvm/CodeGen/PHIElimination.h" @@ -957,7 +958,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses( if (getOptLevel() != CodeGenOptLevel::None && !TM.targetSchedulesPostRAScheduling()) { if (Opt.MISchedPostRA) - addPass(PostMachineSchedulerPass()); + addPass(PostMachineSchedulerPass(&TM)); else addPass(PostRASchedulerPass()); } @@ -1141,7 +1142,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addOptimizedRegAlloc( addPass(RenameIndependentSubregsPass()); // PreRA instruction scheduling. - addPass(MachineSchedulerPass()); + addPass(MachineSchedulerPass(&TM)); if (derived().addRegAssignmentOptimized(addPass)) { // Allow targets to expand pseudo instructions depending on the choice of diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 35199104731d20..85846072f8bca2 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -142,11 +142,13 @@ MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass()) MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass()) MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass()) MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass()) +MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass(TM)) MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass()) MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass()) MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass()) MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass()) MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass()) +MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM)) MACHINE_FUNCTION_PASS("print", PrintMIRPass()) MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs())) MACHINE_FUNCTION_PASS("print<live-intervals>", LiveIntervalsPrinterPass(errs())) @@ -240,14 +242,12 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter) DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass) DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass) DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata) -DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass) DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass) DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass) DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass) DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass) DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass) DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass) -DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass) DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass) DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass) DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass) diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index 0a7937eb1cf973..92f41b7def858b 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeModuloScheduleTestPass(Registry); initializeMachinePostDominatorTreeWrapperPassPass(Registry); initializeMachineRegionInfoPassPass(Registry); - initializeMachineSchedulerPass(Registry); + initializeMachineSchedulerLegacyPass(Registry); initializeMachineSinkingPass(Registry); initializeMachineUniformityAnalysisPassPass(Registry); initializeMachineUniformityInfoPrinterPassPass(Registry); @@ -105,7 +105,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializePHIEliminationPass(Registry); initializePatchableFunctionPass(Registry); initializePeepholeOptimizerLegacyPass(Registry); - initializePostMachineSchedulerPass(Registry); + initializePostMachineSchedulerLegacyPass(Registry); initializePostRAHazardRecognizerPass(Registry); initializePostRAMachineSinkingPass(Registry); initializePostRASchedulerPass(Registry); diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index df568711583186..3219227a6cf164 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -216,67 +216,85 @@ MachineSchedContext::~MachineSchedContext() { namespace { -/// Base class for a machine scheduler class that can run at any point. -class MachineSchedulerBase : public MachineSchedContext, - public MachineFunctionPass { +/// Base class for the machine scheduler classes. +class MachineSchedulerBase : public MachineSchedContext { +protected: + void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags); +}; + +/// Impl class for MachineScheduler. +class MachineSchedulerImpl : public MachineSchedulerBase { + MachineFunctionPass *P = nullptr; + MachineFunctionAnalysisManager *MFAM = nullptr; + public: - MachineSchedulerBase(char &ID): MachineFunctionPass(ID) {} + MachineSchedulerImpl(MachineFunction &Func, MachineFunctionPass *P); + MachineSchedulerImpl(MachineFunction &Func, + MachineFunctionAnalysisManager &MFAM, + const TargetMachine *TargetM); + bool run(); protected: - void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags); + ScheduleDAGInstrs *createMachineScheduler(); }; -/// MachineScheduler runs after coalescing and before register allocation. -class MachineScheduler : public MachineSchedulerBase { +/// Impl class for PostMachineScheduler. +class PostMachineSchedulerImpl : public MachineSchedulerBase { + MachineFunctionPass *P = nullptr; + MachineFunctionAnalysisManager *MFAM = nullptr; + public: - MachineScheduler(); + PostMachineSchedulerImpl(MachineFunction &Func, MachineFunctionPass *P); + PostMachineSchedulerImpl(MachineFunction &Func, + MachineFunctionAnalysisManager &MFAM, + const TargetMachine *TargetM); + bool run(); - void getAnalysisUsage(AnalysisUsage &AU) const override; +protected: + ScheduleDAGInstrs *createPostMachineScheduler(); +}; +/// MachineScheduler runs after coalescing and before register allocation. +class MachineSchedulerLegacy : public MachineFunctionPass { +public: + MachineSchedulerLegacy(); + void getAnalysisUsage(AnalysisUsage &AU) const override; bool runOnMachineFunction(MachineFunction&) override; static char ID; // Class identification, replacement for typeinfo - -protected: - ScheduleDAGInstrs *createMachineScheduler(); }; /// PostMachineScheduler runs after shortly before code emission. -class PostMachineScheduler : public MachineSchedulerBase { +class PostMachineSchedulerLegacy : public MachineFunctionPass { public: - PostMachineScheduler(); - + PostMachineSchedulerLegacy(); void getAnalysisUsage(AnalysisUsage &AU) const override; - bool runOnMachineFunction(MachineFunction&) override; static char ID; // Class identification, replacement for typeinfo - -protected: - ScheduleDAGInstrs *createPostMachineScheduler(); }; } // end anonymous namespace -char MachineScheduler::ID = 0; +char MachineSchedulerLegacy::ID = 0; -char &llvm::MachineSchedulerID = MachineScheduler::ID; +char &llvm::MachineSchedulerID = MachineSchedulerLegacy::ID; -INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE, +INITIALIZE_PASS_BEGIN(MachineSchedulerLegacy, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass) -INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE, +INITIALIZE_PASS_END(MachineSchedulerLegacy, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) -MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) { - initializeMachineSchedulerPass(*PassRegistry::getPassRegistry()); +MachineSchedulerLegacy::MachineSchedulerLegacy() : MachineFunctionPass(ID) { + initializeMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry()); } -void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { +void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addRequired<MachineDominatorTreeWrapperPass>(); AU.addRequired<MachineLoopInfoWrapperPass>(); @@ -289,23 +307,24 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { MachineFunctionPass::getAnalysisUsage(AU); } -char PostMachineScheduler::ID = 0; +char PostMachineSchedulerLegacy::ID = 0; -char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID; +char &llvm::PostMachineSchedulerID = PostMachineSchedulerLegacy::ID; -INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched", +INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched", "PostRA Machine Instruction Scheduler", false, false) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) -INITIALIZE_PASS_END(PostMachineScheduler, "postmisched", +INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched", "PostRA Machine Instruction Scheduler", false, false) -PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) { - initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry()); +PostMachineSchedulerLegacy::PostMachineSchedulerLegacy() + : MachineFunctionPass(ID) { + initializePostMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry()); } -void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { +void PostMachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addRequired<MachineDominatorTreeWrapperPass>(); AU.addRequired<MachineLoopInfoWrapperPass>(); @@ -384,18 +403,40 @@ nextIfDebug(MachineBasicBlock::iterator I, .getNonConstIterator(); } +MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func, + MachineFunctionPass *P) + : P(P) { + MF = &Func; + MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI(); + MDT = &P->getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); + TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>(); + AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults(); + LIS = &P->getAnalysis<LiveIntervalsWrapperPass>().getLIS(); +} + +MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func, + MachineFunctionAnalysisManager &MFAM, + const TargetMachine *TargetM) + : MFAM(&MFAM) { + MF = &Func; + TM = TargetM; + MLI = &MFAM.getResult<MachineLoopAnalysis>(Func); + MDT = &MFAM.getResult<MachineDominatorTreeAnalysis>(Func); + auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func) + .getManager(); + AA = &FAM.getResult<AAManager>(Func.getFunction()); + LIS = &MFAM.getResult<LiveIntervalsAnalysis>(Func); +} + /// Instantiate a ScheduleDAGInstrs that will be owned by the caller. -ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() { +ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() { // Select the scheduler, or set the default. MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt; if (Ctor != useDefaultMachineSched) return Ctor(this); - const TargetMachine &TM = - getAnalysis<TargetPassConfig>().getTM<TargetMachine>(); - // Get the default scheduler set by the target for this function. - ScheduleDAGInstrs *Scheduler = TM.createMachineScheduler(this); + ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this); if (Scheduler) return Scheduler; @@ -403,14 +444,60 @@ ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() { return createGenericSchedLive(this); } +bool MachineSchedulerImpl::run() { + if (VerifyScheduling) { + LLVM_DEBUG(LIS->dump()); + std::string MSchedBanner = "Before machine scheduling."; + if (P) + MF->verify(P, MSchedBanner.c_str(), &errs()); + else + MF->verify(*MFAM, MSchedBanner.c_str(), &errs()); + } + RegClassInfo->runOnMachineFunction(*MF); + + // Instantiate the selected scheduler for this target, function, and + // optimization level. + std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler()); + scheduleRegions(*Scheduler, false); + + LLVM_DEBUG(LIS->dump()); + if (VerifyScheduling) { + std::string MSchedBanner = "After machine scheduling."; + if (P) + MF->verify(P, MSchedBanner.c_str(), &errs()); + else + MF->verify(*MFAM, MSchedBanner.c_str(), &errs()); + } + return true; +} + +PostMachineSchedulerImpl::PostMachineSchedulerImpl(MachineFunction &Func, + MachineFunctionPass *P) + : P(P) { + MF = &Func; + MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI(); + TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>(); + AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults(); +} + +PostMachineSchedulerImpl::PostMachineSchedulerImpl( + MachineFunction &Func, MachineFunctionAnalysisManager &MFAM, + const TargetMachine *TargetM) + : MFAM(&MFAM) { + MF = &Func; + TM = TargetM; + MLI = &MFAM.getResult<MachineLoopAnalysis>(Func); + auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func) + .getManager(); + AA = &FAM.getResult<AAManager>(Func.getFunction()); +} + /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by /// the caller. We don't have a command line option to override the postRA /// scheduler. The Target must configure it. -ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() { - const TargetMachine &TM = - getAnalysis<TargetPassConfig>().getTM<TargetMachine>(); +ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() { // Get the postRA scheduler set by the target for this function. - ScheduleDAGInstrs *Scheduler = TM.createPostMachineScheduler(this); + ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this); if (Scheduler) return Scheduler; @@ -418,6 +505,30 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() { return createGenericSchedPostRA(this); } +bool PostMachineSchedulerImpl::run() { + if (VerifyScheduling) { + std::string PostMSchedBanner = "Before post machine scheduling."; + if (P) + MF->verify(P, PostMSchedBanner.c_str(), &errs()); + else + MF->verify(*MFAM, PostMSchedBanner.c_str(), &errs()); + } + + // Instantiate the selected scheduler for this target, function, and + // optimization level. + std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler()); + scheduleRegions(*Scheduler, true); + + if (VerifyScheduling) { + std::string PostMSchedBanner = "After post machine scheduling."; + if (P) + MF->verify(P, PostMSchedBanner.c_str(), &errs()); + else + MF->verify(*MFAM, PostMSchedBanner.c_str(), &errs()); + } + return true; +} + /// Top-level MachineScheduler pass driver. /// /// Visit blocks in function order. Divide each block into scheduling regions @@ -434,72 +545,84 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() { /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler /// design would be to split blocks at scheduling boundaries, but LLVM has a /// general bias against block splitting purely for implementation simplicity. -bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { - if (skipFunction(mf.getFunction())) +bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(MF.getFunction())) return false; if (EnableMachineSched.getNumOccurrences()) { if (!EnableMachineSched) return false; - } else if (!mf.getSubtarget().enableMachineScheduler()) + } else if (!MF.getSubtarget().enableMachineScheduler()) { return false; + } - LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs())); - - // Initialize the context of the pass. - MF = &mf; - MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI(); - MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); - AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); + LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs())); - LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS(); + MachineSchedulerImpl Impl(MF, this); + return Impl.run(); +} - if (VerifyScheduling) { - LLVM_DEBUG(LIS->dump()); - MF->verify(this, "Before machine scheduling.", &errs()); +PreservedAnalyses +MachineSchedulerPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + if (EnableMachineSched.getNumOccurrences()) { + if (!EnableMachineSched) + return PreservedAnalyses::a... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/125703 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
