llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-systemz Author: None (llvmbot) <details> <summary>Changes</summary> Backport eb1a571114a799f532a12b2f062746d3b92fed88 Requested by: @<!-- -->nikic --- Full diff: https://github.com/llvm/llvm-project/pull/125236.diff 2 Files Affected: - (modified) llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp (+12) - (added) llvm/test/CodeGen/SystemZ/cond-move-10.mir (+21) ``````````diff diff --git a/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp b/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp index e15f9027cc2095..cf3073f0f20904 100644 --- a/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp +++ b/llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp @@ -107,6 +107,18 @@ void SystemZPostRewrite::selectSELRMux(MachineBasicBlock &MBB, bool Src1IsHigh = SystemZ::isHighReg(Src1Reg); bool Src2IsHigh = SystemZ::isHighReg(Src2Reg); + // In rare cases both sources are the same register (after + // machine-cse). This must be handled as it may lead to wrong-code (after + // machine-cp) if the kill flag on Src1 isn't cleared (with + // expandCondMove()). + if (Src1Reg == Src2Reg) { + BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(), + TII->get(SystemZ::COPY), DestReg) + .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1))); + MBBI->eraseFromParent(); + return; + } + // If sources and destination aren't all high or all low, we may be able to // simplify the operation by moving one of the sources to the destination // first. But only if this doesn't clobber the other source. diff --git a/llvm/test/CodeGen/SystemZ/cond-move-10.mir b/llvm/test/CodeGen/SystemZ/cond-move-10.mir new file mode 100644 index 00000000000000..1db960829729ea --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/cond-move-10.mir @@ -0,0 +1,21 @@ +# RUN: llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z15 -run-pass=systemz-post-rewrite \ +# RUN: 2>&1 | FileCheck %s + +# The SELRMux has two identical sources - replace with a copy instruction. +# CHECK: name: fun0 +# CHECK: renamable $r1l = AHIMuxK killed renamable $r1l, -1, implicit-def dead $cc +# CHECK-NEXT: CHIMux renamable $r5h, 9, implicit-def $cc +# CHECK-NEXT: $r14h = COPY killed renamable $r1l +--- +name: fun0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $r1l, $r5h + renamable $r1l = AHIMuxK killed renamable $r1l, -1, implicit-def dead $cc + CHIMux renamable $r5h, 9, implicit-def $cc + renamable $r14h = SELRMux killed renamable $r1l, renamable $r1l, 14, 8, implicit $cc + $r14l = COPY killed renamable $r14h + $r14d = LGFR $r14l + Return implicit $r14d +... `````````` </details> https://github.com/llvm/llvm-project/pull/125236 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
