https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/123943
This is looking at operand 0 of a REG_SEQUENCE, which can never
have a subregister index.
>From 1e96d7ed8b5d108ff50a7f35d725638db23f64a2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Wed, 22 Jan 2025 20:30:30 +0700
Subject: [PATCH] PeepholeOpt: Remove check for subreg index on a def operand
This is looking at operand 0 of a REG_SEQUENCE, which can never
have a subregister index.
---
llvm/lib/CodeGen/PeepholeOptimizer.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index aec4aaa81761c7..48c25d5039bfd4 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -426,8 +426,8 @@ class RegSequenceRewriter : public Rewriter {
const MachineOperand &MODef = CopyLike.getOperand(0);
Dst.Reg = MODef.getReg();
- // If we have to compose sub-registers, bail.
- return MODef.getSubReg() == 0;
+ assert(MODef.getSubReg() == 0 && "cannot have subregister def in SSA");
+ return true;
}
bool RewriteCurrentSource(Register NewReg, unsigned NewSubReg) override {
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