Author: Akshat Oke Date: 2025-01-10T12:22:48+05:30 New Revision: f11be66dcc53b1908f4520772e55d5506253ae27
URL: https://github.com/llvm/llvm-project/commit/f11be66dcc53b1908f4520772e55d5506253ae27 DIFF: https://github.com/llvm/llvm-project/commit/f11be66dcc53b1908f4520772e55d5506253ae27.diff LOG: Revert "Spiller: Detach legacy pass and supply analyses instead (#119181)" This reverts commit a531800344dc54e9c197a13b22e013f919f3f5e1. Added: Modified: llvm/include/llvm/CodeGen/Spiller.h llvm/lib/CodeGen/InlineSpiller.cpp llvm/lib/CodeGen/RegAllocBasic.cpp llvm/lib/CodeGen/RegAllocGreedy.cpp llvm/lib/CodeGen/RegAllocPBQP.cpp Removed: ################################################################################ diff --git a/llvm/include/llvm/CodeGen/Spiller.h b/llvm/include/llvm/CodeGen/Spiller.h index 3132cefeb6c68a..51ad36bc6b1f8b 100644 --- a/llvm/include/llvm/CodeGen/Spiller.h +++ b/llvm/include/llvm/CodeGen/Spiller.h @@ -19,10 +19,6 @@ class MachineFunction; class MachineFunctionPass; class VirtRegMap; class VirtRegAuxInfo; -class LiveIntervals; -class LiveStacks; -class MachineDominatorTree; -class MachineBlockFrequencyInfo; /// Spiller interface. /// @@ -45,20 +41,12 @@ class Spiller { virtual ArrayRef<Register> getReplacedRegs() = 0; virtual void postOptimization() {} - - struct RequiredAnalyses { - LiveIntervals &LIS; - LiveStacks &LSS; - MachineDominatorTree &MDT; - const MachineBlockFrequencyInfo &MBFI; - }; }; /// Create and return a spiller that will insert spill code directly instead /// of deferring though VirtRegMap. -Spiller *createInlineSpiller(const Spiller::RequiredAnalyses &Analyses, - MachineFunction &MF, VirtRegMap &VRM, - VirtRegAuxInfo &VRAI); +Spiller *createInlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, + VirtRegMap &VRM, VirtRegAuxInfo &VRAI); } // end namespace llvm diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index b9768d5c63a5d1..64f290f5930a1b 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -75,6 +75,7 @@ RestrictStatepointRemat("restrict-statepoint-remat", cl::desc("Restrict remat for statepoint operands")); namespace { + class HoistSpillHelper : private LiveRangeEdit::Delegate { MachineFunction &MF; LiveIntervals &LIS; @@ -127,11 +128,15 @@ class HoistSpillHelper : private LiveRangeEdit::Delegate { DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns); public: - HoistSpillHelper(const Spiller::RequiredAnalyses &Analyses, - MachineFunction &mf, VirtRegMap &vrm) - : MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT), + HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf, + VirtRegMap &vrm) + : MF(mf), LIS(pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()), + LSS(pass.getAnalysis<LiveStacksWrapperLegacy>().getLS()), + MDT(pass.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()), VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()), - TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI), + TRI(*mf.getSubtarget().getRegisterInfo()), + MBFI( + pass.getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()), IPA(LIS, mf.getNumBlockIDs()) {} void addToMergeableSpills(MachineInstr &Spill, int StackSlot, @@ -185,12 +190,16 @@ class InlineSpiller : public Spiller { ~InlineSpiller() override = default; public: - InlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF, - VirtRegMap &VRM, VirtRegAuxInfo &VRAI) - : MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT), + InlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap &VRM, + VirtRegAuxInfo &VRAI) + : MF(MF), LIS(Pass.getAnalysis<LiveIntervalsWrapperPass>().getLIS()), + LSS(Pass.getAnalysis<LiveStacksWrapperLegacy>().getLS()), + MDT(Pass.getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()), VRM(VRM), MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()), - TRI(*MF.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI), - HSpiller(Analyses, MF, VRM), VRAI(VRAI) {} + TRI(*MF.getSubtarget().getRegisterInfo()), + MBFI( + Pass.getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()), + HSpiller(Pass, MF, VRM), VRAI(VRAI) {} void spill(LiveRangeEdit &) override; ArrayRef<Register> getSpilledRegs() override { return RegsToSpill; } @@ -228,11 +237,10 @@ Spiller::~Spiller() = default; void Spiller::anchor() {} -Spiller * -llvm::createInlineSpiller(const InlineSpiller::RequiredAnalyses &Analyses, - MachineFunction &MF, VirtRegMap &VRM, - VirtRegAuxInfo &VRAI) { - return new InlineSpiller(Analyses, MF, VRM, VRAI); +Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass, + MachineFunction &MF, VirtRegMap &VRM, + VirtRegAuxInfo &VRAI) { + return new InlineSpiller(Pass, MF, VRM, VRAI); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp index f3f34f890be11e..c05aa1e40e4779 100644 --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -22,7 +22,6 @@ #include "llvm/CodeGen/LiveRegMatrix.h" #include "llvm/CodeGen/LiveStacks.h" #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" -#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/Passes.h" @@ -188,7 +187,6 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<ProfileSummaryInfoWrapperPass>(); AU.addRequired<MachineBlockFrequencyInfoWrapperPass>(); AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>(); - AU.addRequired<MachineDominatorTreeWrapperPass>(); AU.addRequiredID(MachineDominatorsID); AU.addPreservedID(MachineDominatorsID); AU.addRequired<MachineLoopInfoWrapperPass>(); @@ -312,20 +310,16 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) { << "********** Function: " << mf.getName() << '\n'); MF = &mf; - auto &MBFI = getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI(); - auto &LiveStks = getAnalysis<LiveStacksWrapperLegacy>().getLS(); - auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); - RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(), getAnalysis<LiveIntervalsWrapperPass>().getLIS(), getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM()); - VirtRegAuxInfo VRAI(*MF, *LIS, *VRM, - getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI, - &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI()); + VirtRegAuxInfo VRAI( + *MF, *LIS, *VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(), + getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI(), + &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI()); VRAI.calculateSpillWeightsAndHints(); - SpillerInstance.reset( - createInlineSpiller({*LIS, LiveStks, MDT, MBFI}, *MF, *VRM, VRAI)); + SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM, VRAI)); allocatePhysRegs(); postOptimization(); diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 66e9cf546b8379..b94992c20b119a 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -2750,7 +2750,6 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) { Bundles = &getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles(); SpillPlacer = &getAnalysis<SpillPlacementWrapperLegacy>().getResult(); DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV(); - auto &LSS = getAnalysis<LiveStacksWrapperLegacy>().getLS(); initializeCSRCost(); @@ -2771,8 +2770,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) { getAnalysis<RegAllocPriorityAdvisorAnalysis>().getAdvisor(*MF, *this); VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, *VRM, *Loops, *MBFI); - SpillerInstance.reset( - createInlineSpiller({*LIS, LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI)); + SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM, *VRAI)); VRAI->calculateSpillWeightsAndHints(); diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp index e230a1be95c9fa..696c312e4ba00a 100644 --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -794,9 +794,6 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { MachineBlockFrequencyInfo &MBFI = getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI(); - auto &LiveStks = getAnalysis<LiveStacksWrapperLegacy>().getLS(); - auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(); - VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM(); PBQPVirtRegAuxInfo VRAI( @@ -810,7 +807,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { VirtRegAuxInfo DefaultVRAI( MF, LIS, VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI); std::unique_ptr<Spiller> VRegSpiller( - createInlineSpiller({LIS, LiveStks, MDT, MBFI}, MF, VRM, DefaultVRAI)); + createInlineSpiller(*this, MF, VRM, DefaultVRAI)); MF.getRegInfo().freezeReservedRegs(); _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
