https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/117411
>From af7d8913f96f7d92dfe6305add635f78e7f73538 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Fri, 22 Nov 2024 18:40:25 -0800
Subject: [PATCH] AMDGPU: Use isWave[32|64] instead of comparing size value
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 ++--
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 +++---
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 4 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e520dfff1016b2..73ca59fe320d27 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16677,8 +16677,8 @@ SITargetLowering::getRegClassFor(MVT VT, bool
isDivergent) const {
const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT,
false);
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
if (RC == &AMDGPU::VReg_1RegClass && !isDivergent)
- return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass
- : &AMDGPU::SReg_32RegClass;
+ return Subtarget->isWave64() ? &AMDGPU::SReg_64RegClass
+ : &AMDGPU::SReg_32RegClass;
if (!TRI->isSGPRClass(RC) && !isDivergent)
return TRI->getEquivalentSGPRClass(RC);
if (TRI->isSGPRClass(RC) && isDivergent)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 2c30bfcb5522a8..4a94d690297949 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7703,8 +7703,8 @@ void SIInstrInfo::lowerSelect(SIInstrWorklist &Worklist,
MachineInstr &Inst,
// Insert a trivial select instead of creating a copy, because a copy
from
// SCC would semantically mean just copying a single bit, but we may need
// the result to be a vector condition mask that needs preserving.
- unsigned Opcode = (ST.getWavefrontSize() == 64) ? AMDGPU::S_CSELECT_B64
- : AMDGPU::S_CSELECT_B32;
+ unsigned Opcode =
+ ST.isWave64() ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
auto NewSelect =
BuildMI(MBB, MII, DL, get(Opcode), NewCondReg).addImm(-1).addImm(0);
NewSelect->getOperand(3).setIsUndef(Cond.isUndef());
@@ -8716,7 +8716,7 @@ uint64_t SIInstrInfo::getScratchRsrcWords23() const {
}
// IndexStride = 64 / 32.
- uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2;
+ uint64_t IndexStride = ST.isWave64() ? 3 : 2;
Rsrc23 |= IndexStride << AMDGPU::RSRC_INDEX_STRIDE_SHIFT;
// If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 67d9e4138753f7..84cb1e48772cae 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//
-def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
+def isWave32 : Predicate<"Subtarget->isWave32()">,
AssemblerPredicate <(all_of FeatureWavefrontSize32)>;
-def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
+def isWave64 : Predicate<"Subtarget->isWave64()">,
AssemblerPredicate <(all_of FeatureWavefrontSize64)>;
class AMDGPUMnemonicAlias<string From, string To, string VariantName = "">
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