https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/116326
None
>From 9a4813f306f06ab57e9b2568e44056b2daaf59b5 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Mon, 11 Nov 2024 06:40:27 +0000
Subject: [PATCH] [CodeGen][NewPM] Port PeepholeOptimizer to NPM
---
llvm/include/llvm/CodeGen/Passes.h | 2 +-
llvm/include/llvm/CodeGen/PeepholeOptimizer.h | 30 ++++++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/PeepholeOptimizer.cpp | 101 ++++++++++++------
llvm/lib/CodeGen/TargetPassConfig.cpp | 2 +-
llvm/lib/Passes/PassBuilder.cpp | 1 +
.../Target/AArch64/AArch64TargetMachine.cpp | 2 +-
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp | 2 +-
.../CodeGen/AArch64/csinc-cmp-removal.mir | 1 +
.../AMDGPU/fold-immediate-output-mods.mir | 1 +
llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir | 1 +
llvm/test/CodeGen/Lanai/peephole-compare.mir | 1 +
.../test/CodeGen/PowerPC/bitcast-peephole.mir | 1 +
16 files changed, 110 insertions(+), 42 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/PeepholeOptimizer.h
diff --git a/llvm/include/llvm/CodeGen/Passes.h
b/llvm/include/llvm/CodeGen/Passes.h
index 708ff464b38093..7698f557c58a04 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -363,7 +363,7 @@ namespace llvm {
/// PeepholeOptimizer - This pass performs peephole optimizations -
/// like extension and comparison eliminations.
- extern char &PeepholeOptimizerID;
+ extern char &PeepholeOptimizerLegacyID;
/// OptimizePHIs - This pass optimizes machine instruction PHIs
/// to take advantage of opportunities created during DAG legalization.
diff --git a/llvm/include/llvm/CodeGen/PeepholeOptimizer.h
b/llvm/include/llvm/CodeGen/PeepholeOptimizer.h
new file mode 100644
index 00000000000000..2a8af245906dc5
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/PeepholeOptimizer.h
@@ -0,0 +1,30 @@
+//===- llvm/CodeGen/PeepholeOptimizer.h -------------------------*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_PEEPHOLEOPTIMIZER_H
+#define LLVM_CODEGEN_PEEPHOLEOPTIMIZER_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class PeepholeOptimizerPass : public PassInfoMixin<PeepholeOptimizerPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_PEEPHOLEOPTIMIZER_H
+
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 0e166273757552..030b74e3623b3c 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -227,7 +227,7 @@ void initializePEIPass(PassRegistry &);
void initializePHIEliminationPass(PassRegistry &);
void initializePartiallyInlineLibCallsLegacyPassPass(PassRegistry &);
void initializePatchableFunctionPass(PassRegistry &);
-void initializePeepholeOptimizerPass(PassRegistry &);
+void initializePeepholeOptimizerLegacyPass(PassRegistry &);
void initializePhiValuesWrapperPassPass(PassRegistry &);
void initializePhysicalRegisterUsageInfoPass(PassRegistry &);
void initializePlaceBackedgeSafepointsLegacyPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 7fa6fa118fe551..51de9968201d4b 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -52,6 +52,7 @@
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
+#include "llvm/CodeGen/PeepholeOptimizer.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 3ceb5ca7d18eda..b9b50499e90fd0 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -141,6 +141,7 @@ MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass())
+MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
MACHINE_FUNCTION_PASS("print<live-intervals>",
LiveIntervalsPrinterPass(dbgs()))
@@ -237,7 +238,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity",
MachineUniformityInfoWrapperPa
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
-DUMMY_MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass)
DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 39fba1d0b527ef..744b9cdf687037 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -103,7 +103,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePEIPass(Registry);
initializePHIEliminationPass(Registry);
initializePatchableFunctionPass(Registry);
- initializePeepholeOptimizerPass(Registry);
+ initializePeepholeOptimizerLegacyPass(Registry);
initializePostMachineSchedulerPass(Registry);
initializePostRAHazardRecognizerPass(Registry);
initializePostRAMachineSinkingPass(Registry);
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 12b276f01bf3c2..032c4be89468d1 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -65,6 +65,7 @@
// C = copy A <-- same-bank copy
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/PeepholeOptimizer.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
@@ -78,6 +79,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
@@ -147,8 +149,7 @@ namespace {
class ValueTrackerResult;
class RecurrenceInstr;
-class PeepholeOptimizer : public MachineFunctionPass,
- private MachineFunction::Delegate {
+class PeepholeOptimizer : private MachineFunction::Delegate {
const TargetInstrInfo *TII = nullptr;
const TargetRegisterInfo *TRI = nullptr;
MachineRegisterInfo *MRI = nullptr;
@@ -156,30 +157,10 @@ class PeepholeOptimizer : public MachineFunctionPass,
MachineLoopInfo *MLI = nullptr;
public:
- static char ID; // Pass identification
-
- PeepholeOptimizer() : MachineFunctionPass(ID) {
- initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
- }
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- MachineFunctionPass::getAnalysisUsage(AU);
- AU.addRequired<MachineLoopInfoWrapperPass>();
- AU.addPreserved<MachineLoopInfoWrapperPass>();
- if (Aggressive) {
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addPreserved<MachineDominatorTreeWrapperPass>();
- }
- }
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::IsSSA);
- }
+ PeepholeOptimizer(MachineDominatorTree *DT, MachineLoopInfo *MLI)
+ : DT(DT), MLI(MLI) {}
+ bool run(MachineFunction &MF);
/// Track Def -> Use info used for rewriting copies.
using RewriteMapTy = SmallDenseMap<RegSubRegPair, ValueTrackerResult>;
@@ -294,6 +275,33 @@ class PeepholeOptimizer : public MachineFunctionPass,
}
};
+class PeepholeOptimizerLegacy : public MachineFunctionPass {
+public:
+ static char ID; // Pass identification
+
+ PeepholeOptimizerLegacy() : MachineFunctionPass(ID) {
+ initializePeepholeOptimizerLegacyPass(*PassRegistry::getPassRegistry());
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ AU.addRequired<MachineLoopInfoWrapperPass>();
+ AU.addPreserved<MachineLoopInfoWrapperPass>();
+ if (Aggressive) {
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addPreserved<MachineDominatorTreeWrapperPass>();
+ }
+ }
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+};
+
/// Helper class to hold instructions that are inside recurrence cycles.
/// The recurrence cycle is formulated around 1) a def operand and its
/// tied use operand, or 2) a def operand and a use operand that is commutable
@@ -469,16 +477,16 @@ class ValueTracker {
} // end anonymous namespace
-char PeepholeOptimizer::ID = 0;
+char PeepholeOptimizerLegacy::ID = 0;
-char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
+char &llvm::PeepholeOptimizerLegacyID = PeepholeOptimizerLegacy::ID;
-INITIALIZE_PASS_BEGIN(PeepholeOptimizer, DEBUG_TYPE, "Peephole Optimizations",
- false, false)
+INITIALIZE_PASS_BEGIN(PeepholeOptimizerLegacy, DEBUG_TYPE,
+ "Peephole Optimizations", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
-INITIALIZE_PASS_END(PeepholeOptimizer, DEBUG_TYPE, "Peephole Optimizations",
- false, false)
+INITIALIZE_PASS_END(PeepholeOptimizerLegacy, DEBUG_TYPE,
+ "Peephole Optimizations", false, false)
/// If instruction is a copy-like instruction, i.e. it reads a single register
/// and writes a single register and it does not modify the source, and if the
@@ -1644,9 +1652,35 @@ bool PeepholeOptimizer::optimizeRecurrence(MachineInstr
&PHI) {
return Changed;
}
-bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+PeepholeOptimizerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ auto *DT =
+ Aggressive ? &MFAM.getResult<MachineDominatorTreeAnalysis>(MF) : nullptr;
+ auto *MLI = &MFAM.getResult<MachineLoopAnalysis>(MF);
+ PeepholeOptimizer Impl(DT, MLI);
+ bool Changed = Impl.run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserve<MachineDominatorTreeAnalysis>();
+ PA.preserve<MachineLoopAnalysis>();
+ return PA;
+}
+
+bool PeepholeOptimizerLegacy::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
+ auto *DT = Aggressive
+ ? &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()
+ : nullptr;
+ auto *MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ PeepholeOptimizer Impl(DT, MLI);
+ return Impl.run(MF);
+}
+
+bool PeepholeOptimizer::run(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
LLVM_DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
@@ -1657,9 +1691,6 @@ bool
PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
TII = MF.getSubtarget().getInstrInfo();
TRI = MF.getSubtarget().getRegisterInfo();
MRI = &MF.getRegInfo();
- DT = Aggressive ?
&getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree()
- : nullptr;
- MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
MF.setDelegate(this);
bool Changed = false;
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp
b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 249407ff1c921c..a6159a38753cf5 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -1315,7 +1315,7 @@ void TargetPassConfig::addMachineSSAOptimization() {
addPass(&MachineSinkingID);
- addPass(&PeepholeOptimizerID);
+ addPass(&PeepholeOptimizerLegacyID);
// Clean-up the dead code that may have been generated by peephole
// rewriting.
addPass(&DeadMachineInstructionElimID);
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index df7c9a4fbb9387..6582c1994c88e9 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -118,6 +118,7 @@
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
+#include "llvm/CodeGen/PeepholeOptimizer.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/SafeStack.h"
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 074f39c19fdb24..8297f8405845e9 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -810,7 +810,7 @@ void AArch64PassConfig::addPreRegAlloc() {
addPass(createAArch64AdvSIMDScalar());
// The AdvSIMD pass may produce copies that can be rewritten to
// be register coalescer friendly.
- addPass(&PeepholeOptimizerID);
+ addPass(&PeepholeOptimizerLegacyID);
}
if (TM->getOptLevel() != CodeGenOptLevel::None && EnableMachinePipeliner)
addPass(&MachinePipelinerID);
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 9611f5f4f00f0c..b9bbe24eb04534 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -498,6 +498,6 @@ void NVPTXPassConfig::addMachineSSAOptimization() {
addPass(&MachineSinkingID);
printAndVerify("After Machine LICM, CSE and Sinking passes");
- addPass(&PeepholeOptimizerID);
+ addPass(&PeepholeOptimizerLegacyID);
printAndVerify("After codegen peephole optimization pass");
}
diff --git a/llvm/test/CodeGen/AArch64/csinc-cmp-removal.mir
b/llvm/test/CodeGen/AArch64/csinc-cmp-removal.mir
index 2098218d23f33c..81abbbf7a2bc65 100644
--- a/llvm/test/CodeGen/AArch64/csinc-cmp-removal.mir
+++ b/llvm/test/CodeGen/AArch64/csinc-cmp-removal.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=peephole-opt -verify-machineinstrs %s -o
- | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes=peephole-opt -verify-machineinstrs %s -o -
| FileCheck %s
---
name: remove_subswr_after_csincwr
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
b/llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
index f8e8ac8937b2f2..64a4708ae64d7b 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -run-pass peephole-opt -verify-machineinstrs %s -o
- | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -passes peephole-opt -verify-machineinstrs %s -o -
| FileCheck -check-prefix=GCN %s
...
# GCN-LABEL: name: no_fold_imm_madak_mac_clamp_f32
# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
diff --git a/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
b/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
index c277515e0b534c..6832482b9dd9b8 100644
--- a/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
+++ b/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
+# RUN: llc -passes=peephole-opt %s -o - | FileCheck %s
--- |
; ModuleID = '<stdin>'
diff --git a/llvm/test/CodeGen/Lanai/peephole-compare.mir
b/llvm/test/CodeGen/Lanai/peephole-compare.mir
index 10735170ca34cb..04274a2d1efd96 100644
--- a/llvm/test/CodeGen/Lanai/peephole-compare.mir
+++ b/llvm/test/CodeGen/Lanai/peephole-compare.mir
@@ -1,4 +1,5 @@
# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
+# RUN: llc -passes=peephole-opt %s -o - | FileCheck %s
# Test the compare fold peephole.
diff --git a/llvm/test/CodeGen/PowerPC/bitcast-peephole.mir
b/llvm/test/CodeGen/PowerPC/bitcast-peephole.mir
index 15238576362b7c..e797c5d30841f3 100644
--- a/llvm/test/CodeGen/PowerPC/bitcast-peephole.mir
+++ b/llvm/test/CodeGen/PowerPC/bitcast-peephole.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=powerpc64le-linux-gnu -run-pass=peephole-opt
-verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=powerpc64le-linux-gnu -passes=peephole-opt
-verify-machineinstrs -o - %s | FileCheck %s
---
name: bitCast
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
