================
@@ -14520,17 +14520,78 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType
IndexType, SelectionDAG &D
return true;
}
+/// Try to map an integer comparison with size > XLEN to vector instructions
+/// before type legalization splits it up into chunks.
+static SDValue
+combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y, ISD::CondCode CC,
+ const SDLoc &DL, SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget) {
+ assert(ISD::isIntEqualitySetCC(CC) && "Bad comparison predicate");
+
+ if (!Subtarget.hasVInstructions())
+ return SDValue();
+
+ MVT XLenVT = Subtarget.getXLenVT();
+ EVT OpVT = X.getValueType();
+ // We're looking for an oversized integer equality comparison.
+ if (OpVT.isScalableVT() || !OpVT.isScalarInteger())
+ return SDValue();
+
+ unsigned OpSize = OpVT.getSizeInBits();
+ // TODO: Support non-power-of-2 types.
+ if (!isPowerOf2_32(OpSize))
+ return SDValue();
+
+ // The size should be larger than XLen and smaller than the maximum vector
+ // size.
+ if (OpSize <= Subtarget.getXLen() ||
+ OpSize > Subtarget.getRealMinVLen() *
+ Subtarget.getMaxLMULForFixedLengthVectors())
+ return SDValue();
+
+ // Don't perform this combine if constructing the vector will be expensive.
+ auto IsVectorBitCastCheap = [](SDValue X) {
+ X = peekThroughBitcasts(X);
+ return isa<ConstantSDNode>(X) || X.getValueType().isVector() ||
+ X.getOpcode() == ISD::LOAD;
+ };
+ if (!IsVectorBitCastCheap(X) || !IsVectorBitCastCheap(Y))
+ return SDValue();
+
+ if (DAG.getMachineFunction().getFunction().hasFnAttribute(
+ Attribute::NoImplicitFloat))
+ return SDValue();
----------------
lukel97 wrote:
Oh that's right noimplicitfloat also disables SIMD, I forgot about that.
https://github.com/llvm/llvm-project/pull/114517
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