llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-transforms Author: Vitaly Buka (vitalybuka) <details> <summary>Changes</summary> --- Patch is 59.63 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113201.diff 3 Files Affected: - (modified) llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp (+23-40) - (modified) llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll (+183-423) - (modified) llvm/test/Instrumentation/MemorySanitizer/pr32842.ll (+10-26) ``````````diff diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 440413b8c2684f..962d7cc5bca347 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -2694,40 +2694,6 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> { setOriginForNaryOp(I); } - /// Build the lowest possible value of V, taking into account V's - /// uninitialized bits. - Value *getLowestPossibleValue(IRBuilder<> &IRB, Value *A, Value *Sa, - bool isSigned) { - if (isSigned) { - // Split shadow into sign bit and other bits. - Value *SaOtherBits = IRB.CreateLShr(IRB.CreateShl(Sa, 1), 1); - Value *SaSignBit = IRB.CreateXor(Sa, SaOtherBits); - // Maximise the undefined shadow bit, minimize other undefined bits. - return IRB.CreateOr(IRB.CreateAnd(A, IRB.CreateNot(SaOtherBits)), - SaSignBit); - } else { - // Minimize undefined bits. - return IRB.CreateAnd(A, IRB.CreateNot(Sa)); - } - } - - /// Build the highest possible value of V, taking into account V's - /// uninitialized bits. - Value *getHighestPossibleValue(IRBuilder<> &IRB, Value *A, Value *Sa, - bool isSigned) { - if (isSigned) { - // Split shadow into sign bit and other bits. - Value *SaOtherBits = IRB.CreateLShr(IRB.CreateShl(Sa, 1), 1); - Value *SaSignBit = IRB.CreateXor(Sa, SaOtherBits); - // Minimise the undefined shadow bit, maximise other undefined bits. - return IRB.CreateOr(IRB.CreateAnd(A, IRB.CreateNot(SaSignBit)), - SaOtherBits); - } else { - // Maximize undefined bits. - return IRB.CreateOr(A, Sa); - } - } - /// Instrument relational comparisons. /// /// This function does exact shadow propagation for all relational @@ -2750,12 +2716,29 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> { // its undefined bits. Let [b0, b1] be the interval of possible values of B. // Then (A cmp B) is defined iff (a0 cmp b1) == (a1 cmp b0). bool IsSigned = I.isSigned(); - Value *S1 = IRB.CreateICmp(I.getPredicate(), - getLowestPossibleValue(IRB, A, Sa, IsSigned), - getHighestPossibleValue(IRB, B, Sb, IsSigned)); - Value *S2 = IRB.CreateICmp(I.getPredicate(), - getHighestPossibleValue(IRB, A, Sa, IsSigned), - getLowestPossibleValue(IRB, B, Sb, IsSigned)); + + auto GetMinMaxUnsigned = [&](Value *V, Value *S) { + if (IsSigned) { + // Map from signed range to unsigned range. Relation A vs B should be + // preserved if checked with `getUnsignedPredicate()`. + // Calcualting Amin, Amax, Bmin, Bmax also will not be affected, as they + // are created by effectively adding/substructing from A or B a value, + // derived from shadow, which can't result in overflow. + APInt MinVal = + APInt::getSignedMinValue(V->getType()->getScalarSizeInBits()); + V = IRB.CreateXor(V, ConstantInt::get(V->getType(), MinVal)); + } + // Minimize undefined bits. + Value *Min = IRB.CreateAnd(V, IRB.CreateNot(S)); + Value *Max = IRB.CreateOr(V, S); + return std::make_pair(Min, Max); + }; + + auto [Amin, Amax] = GetMinMaxUnsigned(A, Sa); + auto [Bmin, Bmax] = GetMinMaxUnsigned(B, Sb); + Value *S1 = IRB.CreateICmp(I.getUnsignedPredicate(), Amin, Bmax); + Value *S2 = IRB.CreateICmp(I.getUnsignedPredicate(), Amax, Bmin); + Value *Si = IRB.CreateXor(S1, S2); setShadow(&I, Si); setOriginForNaryOp(I); diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll index 7aeb763b309048..8746f7f19023e4 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll @@ -1622,20 +1622,12 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i32 [[TMP7]], 0 -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP11]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp slt i32 [[TMP14]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i32 [[TMP4]], -2147483648 +; CHECK-NEXT: [[TMP15:%.*]] = icmp ult i32 [[TMP5]], -2147483648 ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp slt i32 [[X]], 0 ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -1646,20 +1638,12 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0 -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP15]], 0 +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP5]], -2147483648 +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ult i32 [[TMP6]], -2147483648 ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp slt i32 [[X]], 0 ; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -1671,20 +1655,12 @@ define zeroext i1 @ICmpSLTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0 -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp slt i32 [[TMP15]], 0 +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP5]], -2147483648 +; CALLS-NEXT: [[TMP16:%.*]] = icmp ult i32 [[TMP6]], -2147483648 ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp slt i32 [[X]], 0 ; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -1701,20 +1677,12 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP4]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sge i32 [[TMP7]], 0 -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP11]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP10]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sge i32 [[TMP14]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp uge i32 [[TMP4]], -2147483648 +; CHECK-NEXT: [[TMP15:%.*]] = icmp uge i32 [[TMP5]], -2147483648 ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i32 [[X]], 0 ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -1725,20 +1693,12 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sge i32 [[TMP8]], 0 -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP15]], 0 +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp uge i32 [[TMP5]], -2147483648 +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp uge i32 [[TMP6]], -2147483648 ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp sge i32 [[X]], 0 ; ORIGIN-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -1750,20 +1710,12 @@ define zeroext i1 @ICmpSGEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP5]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp sge i32 [[TMP8]], 0 -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP12]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP11]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp sge i32 [[TMP15]], 0 +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp uge i32 [[TMP5]], -2147483648 +; CALLS-NEXT: [[TMP16:%.*]] = icmp uge i32 [[TMP6]], -2147483648 ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp sge i32 [[X]], 0 ; CALLS-NEXT: store i1 [[TMP17]], ptr @__msan_retval_tls, align 8 @@ -1780,20 +1732,12 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i32 0, [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt i32 0, [[TMP14]] +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i32 -2147483648, [[TMP5]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp ugt i32 -2147483648, [[TMP4]] ; CHECK-NEXT: [[TMP16:%.*]] = xor i1 [[TMP8]], [[TMP15]] ; CHECK-NEXT: [[TMP17:%.*]] = icmp sgt i32 0, [[X]] ; CHECK-NEXT: store i1 [[TMP16]], ptr @__msan_retval_tls, align 8 @@ -1804,20 +1748,12 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGIN-NEXT: call void @llvm.donothing() -; ORIGIN-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; ORIGIN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; ORIGIN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; ORIGIN-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; ORIGIN-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; ORIGIN-NEXT: [[TMP9:%.*]] = icmp sgt i32 0, [[TMP8]] -; ORIGIN-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; ORIGIN-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; ORIGIN-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; ORIGIN-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; ORIGIN-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; ORIGIN-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; ORIGIN-NEXT: [[TMP16:%.*]] = icmp sgt i32 0, [[TMP15]] +; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; ORIGIN-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; ORIGIN-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; ORIGIN-NEXT: [[TMP9:%.*]] = icmp ugt i32 -2147483648, [[TMP6]] +; ORIGIN-NEXT: [[TMP16:%.*]] = icmp ugt i32 -2147483648, [[TMP5]] ; ORIGIN-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; ORIGIN-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; ORIGIN-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -1831,20 +1767,12 @@ define zeroext i1 @ICmpSGTZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CALLS-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CALLS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CALLS-NEXT: call void @llvm.donothing() -; CALLS-NEXT: [[TMP3:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 1 -; CALLS-NEXT: [[TMP5:%.*]] = xor i32 [[TMP1]], [[TMP4]] -; CALLS-NEXT: [[TMP6:%.*]] = xor i32 [[TMP5]], -1 -; CALLS-NEXT: [[TMP7:%.*]] = and i32 [[X]], [[TMP6]] -; CALLS-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP4]] -; CALLS-NEXT: [[TMP9:%.*]] = icmp sgt i32 0, [[TMP8]] -; CALLS-NEXT: [[TMP10:%.*]] = shl i32 [[TMP1]], 1 -; CALLS-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP10]], 1 -; CALLS-NEXT: [[TMP12:%.*]] = xor i32 [[TMP1]], [[TMP11]] -; CALLS-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 -; CALLS-NEXT: [[TMP14:%.*]] = and i32 [[X]], [[TMP13]] -; CALLS-NEXT: [[TMP15:%.*]] = or i32 [[TMP14]], [[TMP12]] -; CALLS-NEXT: [[TMP16:%.*]] = icmp sgt i32 0, [[TMP15]] +; CALLS-NEXT: [[TMP3:%.*]] = xor i32 [[X]], -2147483648 +; CALLS-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], -1 +; CALLS-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], [[TMP4]] +; CALLS-NEXT: [[TMP6:%.*]] = or i32 [[TMP3]], [[TMP1]] +; CALLS-NEXT: [[TMP9:%.*]] = icmp ugt i32 -2147483648, [[TMP6]] +; CALLS-NEXT: [[TMP16:%.*]] = icmp ugt i32 -2147483648, [[TMP5]] ; CALLS-NEXT: [[TMP17:%.*]] = xor i1 [[TMP9]], [[TMP16]] ; CALLS-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP1]], 0 ; CALLS-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP2]], i32 0 @@ -1863,20 +1791,12 @@ define zeroext i1 @ICmpSLEZero(i32 %x) nounwind uwtable readnone sanitize_memory ; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP1]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], -1 -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[X]], [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP3]] -; CHECK-NEXT: [[TMP8:%.*]] = icmp sle i32 0, [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 1 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP1]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1 -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[X]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = or i32 [[TMP13]], [[TMP11]] -; CHECK-NEXT: [[TMP15:%.*]] = icmp sle i32 0, [[TMP14]] +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[X]], -2147483648 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ule i32 -2147483648, [[TMP5... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/113201 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
