================
@@ -69,3 +72,38 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI,
Register Reg,
return std::pair(Reg, 0);
}
+
+IntrinsicLaneMaskAnalyzer::IntrinsicLaneMaskAnalyzer(MachineFunction &MF)
+ : MRI(MF.getRegInfo()) {
+ initLaneMaskIntrinsics(MF);
+}
+
+bool IntrinsicLaneMaskAnalyzer::isS32S64LaneMask(Register Reg) {
+ return S32S64LaneMask.contains(Reg);
+}
+
+void IntrinsicLaneMaskAnalyzer::initLaneMaskIntrinsics(MachineFunction &MF) {
+ for (auto &MBB : MF) {
+ for (auto &MI : MBB) {
+ if (MI.getOpcode() == AMDGPU::G_INTRINSIC &&
+ MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID() ==
+ Intrinsic::amdgcn_if_break) {
+ S32S64LaneMask.insert(MI.getOperand(3).getReg());
+ findLCSSAPhi(MI.getOperand(0).getReg());
+ }
+
+ if (MI.getOpcode() == AMDGPU::SI_IF ||
+ MI.getOpcode() == AMDGPU::SI_ELSE) {
+ findLCSSAPhi(MI.getOperand(0).getReg());
+ }
+ }
+ }
+}
+
+void IntrinsicLaneMaskAnalyzer::findLCSSAPhi(Register Reg) {
+ S32S64LaneMask.insert(Reg);
+ for (auto &LCSSAPhi : MRI.use_instructions(Reg)) {
----------------
arsenm wrote:
```suggestion
for (const MachineInstr &LCSSAPhi : MRI.use_instructions(Reg)) {
```
https://github.com/llvm/llvm-project/pull/112863
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