================
@@ -54,9 +54,28 @@ const MachineBasicBlock
*MachineSSAContext::getDefBlock(Register value) const {
return F->getRegInfo().getVRegDef(value)->getParent();
}
+static bool isUndef(const MachineInstr &MI) {
+ return MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+ MI.getOpcode() == TargetOpcode::IMPLICIT_DEF;
+}
+
+/// MachineInstr equivalent of PHINode::hasConstantOrUndefValue()
template <>
-bool MachineSSAContext::isConstantOrUndefValuePhi(const MachineInstr &Phi) {
- return Phi.isConstantValuePHI();
+bool MachineSSAContext::isConstantOrUndefValuePhi(const MachineInstr &MI) {
+ if (!MI.isPHI())
+ return false;
+ const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
+ Register This = MI.getOperand(0).getReg();
+ Register ConstantValue;
+ for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
+ Register Incoming = MI.getOperand(i).getReg();
+ if (Incoming != This && !isUndef(*MRI.getVRegDef(Incoming))) {
----------------
arsenm wrote:
While we should eventually disallow undef operands in all SSA MIR, the current
verifier rules effectively only guarantee this for G_PHI. Regular PHI may
appear at some point with an undef operand, and getVRegDef can fail
https://github.com/llvm/llvm-project/pull/112866
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