https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/108288
Backport 866b93e6b33fac9a4bc62bbc32199bd98f434784
Requested by: @jonathonpenix
>From e9246648ae352b514bad7570f0509b1337217619 Mon Sep 17 00:00:00 2001
From: Jonathon Penix <jpe...@quicinc.com>
Date: Wed, 11 Sep 2024 09:53:11 -0700
Subject: [PATCH] [RISCV] Don't outline pcrel_lo when the function has a
section prefix (#107943)
GNU ld will error when encountering a pcrel_lo whose corresponding
pcrel_hi is in a different section. [1] introduced a check to help
prevent this issue by preventing outlining in a few circumstances.
However, we can also hit this same issue when outlining from functions
with prefixes ("hot"/"unlikely"/"unknown" from profile information, for
example) as the outlined function might not have the same prefix,
possibly resulting in a "paired" pcrel_lo and pcrel_hi ending up in
different sections.
To prevent this issue, take a similar approach as [1] and additionally
prevent outlining when we see a pcrel_lo and the function has a prefix.
[1]
https://github.com/llvm/llvm-project/commit/96c85f80f0d615ffde0f85d8270e0a8c9f4e5430
Fixes #107520
(cherry picked from commit 866b93e6b33fac9a4bc62bbc32199bd98f434784)
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +-
.../RISCV/machineoutliner-pcrel-lo.mir | 104 +++++++++++++++++-
2 files changed, 99 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index ba3b4bd701d634..6c0cbeadebf431 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2902,7 +2902,7 @@
RISCVInstrInfo::getOutliningTypeImpl(MachineBasicBlock::iterator &MBBI,
// if any possible.
if (MO.getTargetFlags() == RISCVII::MO_PCREL_LO &&
(MI.getMF()->getTarget().getFunctionSections() || F.hasComdat() ||
- F.hasSection()))
+ F.hasSection() || F.getSectionPrefix()))
return outliner::InstrType::Illegal;
}
diff --git a/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
b/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
index 8a83543b0280fd..fd3630bcfad256 100644
--- a/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
+++ b/llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir
@@ -18,6 +18,9 @@
define i32 @foo2(i32 %a, i32 %b) comdat { ret i32 0 }
define i32 @foo3(i32 %a, i32 %b) section ".abc" { ret i32 0 }
+
+ define i32 @foo4(i32 %a, i32 %b) !section_prefix !0 { ret i32 0 }
+ !0 = !{!"function_section_prefix", !"myprefix"}
...
---
name: foo
@@ -27,23 +30,24 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11, implicit $x13
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: PseudoRET
+ ;
; CHECK-FS-LABEL: name: foo
; CHECK-FS: bb.0:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
@@ -109,26 +113,27 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
; CHECK-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
; CHECK-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: liveins: $x10, $x11, $x13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
; CHECK-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: PseudoRET
+ ;
; CHECK-FS-LABEL: name: foo2
; CHECK-FS: bb.0:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
@@ -223,6 +228,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: PseudoRET
+ ;
; CHECK-FS-LABEL: name: foo3
; CHECK-FS: bb.0:
; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
@@ -289,3 +295,89 @@ body: |
bb.3:
PseudoRET
...
+---
+name: foo4
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: foo4
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: liveins: $x10, $x11, $x13
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
+ ; CHECK-NEXT: PseudoBR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: liveins: $x10, $x11, $x13
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
+ ; CHECK-NEXT: PseudoBR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: liveins: $x10, $x11, $x13
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
+ ; CHECK-NEXT: PseudoBR %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: PseudoRET
+ ;
+ ; CHECK-FS-LABEL: name: foo4
+ ; CHECK-FS: bb.0:
+ ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
+ ; CHECK-FS-NEXT: {{ $}}
+ ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
+ ; CHECK-FS-NEXT: PseudoBR %bb.3
+ ; CHECK-FS-NEXT: {{ $}}
+ ; CHECK-FS-NEXT: bb.1:
+ ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
+ ; CHECK-FS-NEXT: {{ $}}
+ ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
+ ; CHECK-FS-NEXT: PseudoBR %bb.3
+ ; CHECK-FS-NEXT: {{ $}}
+ ; CHECK-FS-NEXT: bb.2:
+ ; CHECK-FS-NEXT: liveins: $x10, $x11, $x13
+ ; CHECK-FS-NEXT: {{ $}}
+ ; CHECK-FS-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call)
@OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11,
implicit-def $x12, implicit $x10, implicit $x11
+ ; CHECK-FS-NEXT: $x11 = LW killed renamable $x13,
target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1> :: (dereferenceable load
(s32) from @bar)
+ ; CHECK-FS-NEXT: PseudoBR %bb.3
+ ; CHECK-FS-NEXT: {{ $}}
+ ; CHECK-FS-NEXT: bb.3:
+ ; CHECK-FS-NEXT: PseudoRET
+ bb.0:
+ liveins: $x10, $x11, $x13
+
+ $x11 = ORI $x11, 1023
+ $x12 = ADDI $x10, 17
+ $x11 = AND $x12, $x11
+ $x10 = SUB $x10, $x11
+ $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol
.Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
+ PseudoBR %bb.3
+
+ bb.1:
+ liveins: $x10, $x11, $x13
+
+ $x11 = ORI $x11, 1023
+ $x12 = ADDI $x10, 17
+ $x11 = AND $x12, $x11
+ $x10 = SUB $x10, $x11
+ $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol
.Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
+ PseudoBR %bb.3
+
+ bb.2:
+ liveins: $x10, $x11, $x13
+
+ $x11 = ORI $x11, 1023
+ $x12 = ADDI $x10, 17
+ $x11 = AND $x12, $x11
+ $x10 = SUB $x10, $x11
+ $x11 = LW killed renamable $x13, target-flags(riscv-pcrel-lo) <mcsymbol
.Lpcrel_hi1> :: (dereferenceable load (s32) from @bar)
+ PseudoBR %bb.3
+
+ bb.3:
+ PseudoRET
+...
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