Author: ronlieb Date: 2024-09-01T15:47:23-04:00 New Revision: a333954a2198ee3817ba89853a29c3fbee1f7705
URL: https://github.com/llvm/llvm-project/commit/a333954a2198ee3817ba89853a29c3fbee1f7705 DIFF: https://github.com/llvm/llvm-project/commit/a333954a2198ee3817ba89853a29c3fbee1f7705.diff LOG: Revert " [InstCombine] Replace all dominated uses of condition with constants…" This reverts commit 380fa875ab050293be6c8723d770700100b10b8f. Added: Modified: llvm/lib/Transforms/InstCombine/InstructionCombining.cpp llvm/test/Transforms/InstCombine/assume.ll llvm/test/Transforms/InstCombine/branch.ll llvm/test/Transforms/InstCombine/compare-unescaped.ll llvm/test/Transforms/InstCombine/icmp-dom.ll llvm/test/Transforms/InstCombine/indexed-gep-compares.ll llvm/test/Transforms/InstCombine/known-bits.ll llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll llvm/test/Transforms/InstCombine/phi.ll llvm/test/Transforms/InstCombine/pr44245.ll llvm/test/Transforms/InstCombine/sink-into-ncd.ll llvm/test/Transforms/InstCombine/sink_to_unreachable.ll llvm/test/Transforms/InstCombine/zext-phi.ll llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll Removed: llvm/test/Transforms/PhaseOrdering/branch-dom-cond.ll ################################################################################ diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index 866e5f8a00b52d..8a96d1d0fb4c90 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -3705,23 +3705,6 @@ Instruction *InstCombinerImpl::visitBranchInst(BranchInst &BI) { return nullptr; } - // Replace all dominated uses of the condition with true/false - if (BI.getSuccessor(0) != BI.getSuccessor(1)) { - for (auto &U : make_early_inc_range(Cond->uses())) { - BasicBlockEdge Edge0(BI.getParent(), BI.getSuccessor(0)); - if (DT.dominates(Edge0, U)) { - replaceUse(U, ConstantInt::getTrue(Cond->getType())); - addToWorklist(cast<Instruction>(U.getUser())); - continue; - } - BasicBlockEdge Edge1(BI.getParent(), BI.getSuccessor(1)); - if (DT.dominates(Edge1, U)) { - replaceUse(U, ConstantInt::getFalse(Cond->getType())); - addToWorklist(cast<Instruction>(U.getUser())); - } - } - } - DC.registerBranch(&BI); return nullptr; } diff --git a/llvm/test/Transforms/InstCombine/assume.ll b/llvm/test/Transforms/InstCombine/assume.ll index a728c294628cad..474da9968b66ad 100644 --- a/llvm/test/Transforms/InstCombine/assume.ll +++ b/llvm/test/Transforms/InstCombine/assume.ll @@ -485,7 +485,7 @@ define i1 @nonnull3B(ptr %a, i1 %control) { ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) [ "nonnull"(ptr [[LOAD]]) ] ; CHECK-NEXT: ret i1 [[CMP]] ; CHECK: not_taken: -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: ret i1 [[CONTROL]] ; entry: %load = load ptr, ptr %a @@ -513,7 +513,7 @@ define i1 @nonnull3C(ptr %a, i1 %control) { ; CHECK: exit: ; CHECK-NEXT: ret i1 [[CMP2]] ; CHECK: not_taken: -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: ret i1 [[CONTROL]] ; entry: %load = load ptr, ptr %a @@ -543,7 +543,7 @@ define i1 @nonnull3D(ptr %a, i1 %control) { ; CHECK: exit: ; CHECK-NEXT: ret i1 [[CMP2]] ; CHECK: not_taken: -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: ret i1 [[CONTROL]] ; entry: %load = load ptr, ptr %a diff --git a/llvm/test/Transforms/InstCombine/branch.ll b/llvm/test/Transforms/InstCombine/branch.ll index 1d5ff72eef9ce6..1110d5f90b1790 100644 --- a/llvm/test/Transforms/InstCombine/branch.ll +++ b/llvm/test/Transforms/InstCombine/branch.ll @@ -242,99 +242,3 @@ t: f: ret i32 3 } - -define i32 @dom_true(i1 %cmp) { -; CHECK-LABEL: @dom_true( -; CHECK-NEXT: br i1 [[CMP:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: ret i32 1 -; CHECK: if.else: -; CHECK-NEXT: ret i32 0 -; - br i1 %cmp, label %if.then, label %if.else - -if.then: - %zext = zext i1 %cmp to i32 - ret i32 %zext - -if.else: - ret i32 0 -} - -define i32 @dom_false(i1 %cmp) { -; CHECK-LABEL: @dom_false( -; CHECK-NEXT: br i1 [[CMP:%.*]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]] -; CHECK: if.then: -; CHECK-NEXT: ret i32 0 -; CHECK: if.else: -; CHECK-NEXT: ret i32 0 -; - br i1 %cmp, label %if.else, label %if.then - -if.then: - %zext = zext i1 %cmp to i32 - ret i32 %zext - -if.else: - ret i32 0 -} - -define i32 @dom_true_phi(i1 %cmp) { -; CHECK-LABEL: @dom_true_phi( -; CHECK-NEXT: br i1 [[CMP:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: br label [[IF_END:%.*]] -; CHECK: if.else: -; CHECK-NEXT: br label [[IF_END]] -; CHECK: if.end: -; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 -; CHECK-NEXT: ret i32 [[ZEXT]] -; - br i1 %cmp, label %if.then, label %if.else - -if.then: - br label %if.end - -if.else: - br label %if.end - -if.end: - %phi = phi i1 [ true, %if.then ], [ %cmp, %if.else ] - %zext = zext i1 %phi to i32 - ret i32 %zext -} - -; Negative tests - -define i32 @same_dest(i1 %cmp) { -; CHECK-LABEL: @same_dest( -; CHECK-NEXT: br i1 false, label [[IF_THEN:%.*]], label [[IF_THEN]] -; CHECK: if.then: -; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP:%.*]] to i32 -; CHECK-NEXT: ret i32 [[ZEXT]] -; - br i1 %cmp, label %if.then, label %if.then - -if.then: - %zext = zext i1 %cmp to i32 - ret i32 %zext -} - -define i32 @not_dom(i1 %cmp) { -; CHECK-LABEL: @not_dom( -; CHECK-NEXT: br i1 [[CMP:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: br label [[IF_ELSE]] -; CHECK: if.else: -; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 -; CHECK-NEXT: ret i32 [[ZEXT]] -; - br i1 %cmp, label %if.then, label %if.else - -if.then: - br label %if.else - -if.else: - %zext = zext i1 %cmp to i32 - ret i32 %zext -} diff --git a/llvm/test/Transforms/InstCombine/compare-unescaped.ll b/llvm/test/Transforms/InstCombine/compare-unescaped.ll index 02eb464c814c81..ab380c00f82641 100644 --- a/llvm/test/Transforms/InstCombine/compare-unescaped.ll +++ b/llvm/test/Transforms/InstCombine/compare-unescaped.ll @@ -86,7 +86,7 @@ define i1 @compare_and_call_after() { ; CHECK-NEXT: call void @escape(ptr [[M]]) ; CHECK-NEXT: ret i1 true ; CHECK: just_return: -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: ret i1 [[CMP]] ; %m = call ptr @malloc(i64 24) %lgp = load ptr, ptr @gp, align 8, !nonnull !0 diff --git a/llvm/test/Transforms/InstCombine/icmp-dom.ll b/llvm/test/Transforms/InstCombine/icmp-dom.ll index 3cf3a7af77041c..83cedd5ea9cb45 100644 --- a/llvm/test/Transforms/InstCombine/icmp-dom.ll +++ b/llvm/test/Transforms/InstCombine/icmp-dom.ll @@ -196,7 +196,7 @@ define i1 @trueblock_cmp_is_false(i32 %x, i32 %y) { ; CHECK: t: ; CHECK-NEXT: ret i1 false ; CHECK: f: -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: ret i1 [[CMP]] ; entry: %cmp = icmp sgt i32 %x, %y @@ -216,7 +216,7 @@ define i1 @trueblock_cmp_is_false_commute(i32 %x, i32 %y) { ; CHECK: t: ; CHECK-NEXT: ret i1 false ; CHECK: f: -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: ret i1 [[CMP]] ; entry: %cmp = icmp eq i32 %x, %y @@ -236,7 +236,7 @@ define i1 @trueblock_cmp_is_true(i32 %x, i32 %y) { ; CHECK: t: ; CHECK-NEXT: ret i1 true ; CHECK: f: -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: ret i1 [[CMP]] ; entry: %cmp = icmp ult i32 %x, %y @@ -256,7 +256,7 @@ define i1 @trueblock_cmp_is_true_commute(i32 %x, i32 %y) { ; CHECK: t: ; CHECK-NEXT: ret i1 true ; CHECK: f: -; CHECK-NEXT: ret i1 false +; CHECK-NEXT: ret i1 [[CMP]] ; entry: %cmp = icmp ugt i32 %x, %y @@ -271,10 +271,10 @@ f: define i1 @falseblock_cmp_is_false(i32 %x, i32 %y) { ; CHECK-LABEL: @falseblock_cmp_is_false( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: br i1 [[CMP_NOT]], label [[F:%.*]], label [[T:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]] ; CHECK: t: -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: ret i1 [[CMP]] ; CHECK: f: ; CHECK-NEXT: ret i1 false ; @@ -294,7 +294,7 @@ define i1 @falseblock_cmp_is_false_commute(i32 %x, i32 %y) { ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]] ; CHECK: t: -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: ret i1 [[CMP]] ; CHECK: f: ; CHECK-NEXT: ret i1 false ; @@ -314,7 +314,7 @@ define i1 @falseblock_cmp_is_true(i32 %x, i32 %y) { ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]] ; CHECK: t: -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: ret i1 [[CMP]] ; CHECK: f: ; CHECK-NEXT: ret i1 true ; @@ -334,7 +334,7 @@ define i1 @falseblock_cmp_is_true_commute(i32 %x, i32 %y) { ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]] ; CHECK: t: -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: ret i1 [[CMP]] ; CHECK: f: ; CHECK-NEXT: ret i1 true ; diff --git a/llvm/test/Transforms/InstCombine/indexed-gep-compares.ll b/llvm/test/Transforms/InstCombine/indexed-gep-compares.ll index ef8f5fea4ff7c1..2b5b3fce705354 100644 --- a/llvm/test/Transforms/InstCombine/indexed-gep-compares.ll +++ b/llvm/test/Transforms/InstCombine/indexed-gep-compares.ll @@ -292,7 +292,7 @@ define i1 @test7() { ; CHECK-NEXT: [[CMP:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ true, [[BB7]] ] ; CHECK-NEXT: br i1 [[CMP]], label [[BB10:%.*]], label [[BB7]] ; CHECK: bb10: -; CHECK-NEXT: ret i1 true +; CHECK-NEXT: ret i1 [[CMP]] ; entry: br label %bb7 diff --git a/llvm/test/Transforms/InstCombine/known-bits.ll b/llvm/test/Transforms/InstCombine/known-bits.ll index 8cfb987e422f38..3482a8e9759929 100644 --- a/llvm/test/Transforms/InstCombine/known-bits.ll +++ b/llvm/test/Transforms/InstCombine/known-bits.ll @@ -1664,9 +1664,11 @@ define i64 @pr92084(double %x) { ; CHECK-NEXT: [[CMP:%.*]] = fcmp uno double [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN1:%.*]], label [[IF_ELSE:%.*]] ; CHECK: if.then1: -; CHECK-NEXT: br i1 true, label [[IF_ELSE]], label [[IF_THEN2:%.*]] +; CHECK-NEXT: br i1 [[CMP]], label [[IF_ELSE]], label [[IF_THEN2:%.*]] ; CHECK: if.then2: -; CHECK-NEXT: ret i64 poison +; CHECK-NEXT: [[CAST:%.*]] = bitcast double [[X]] to i64 +; CHECK-NEXT: [[AND:%.*]] = and i64 [[CAST]], 1 +; CHECK-NEXT: ret i64 [[AND]] ; CHECK: if.else: ; CHECK-NEXT: ret i64 0 ; diff --git a/llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll b/llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll index 6a054688753500..a9ebcf629a4029 100644 --- a/llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll +++ b/llvm/test/Transforms/InstCombine/phi-known-bits-operand-order.ll @@ -16,8 +16,7 @@ define void @phi_recurrence_start_first() { ; CHECK-NEXT: br i1 [[COND_V]], label [[IF_THEN:%.*]], label [[WHILE_END:%.*]] ; CHECK: if.then: ; CHECK-NEXT: [[START]] = add nuw nsw i32 [[CELL_0]], 1 -; CHECK-NEXT: [[COND_V2:%.*]] = call i1 @cond() -; CHECK-NEXT: br i1 [[COND_V2]], label [[FOR_COND11:%.*]], label [[FOR_COND26]] +; CHECK-NEXT: br i1 [[COND_V]], label [[FOR_COND11:%.*]], label [[FOR_COND26]] ; CHECK: for.cond11: ; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[START]], [[IF_THEN]] ], [ [[STEP:%.*]], [[FOR_COND11]] ] ; CHECK-NEXT: [[CMP13:%.*]] = icmp ult i32 [[I_1]], 100 @@ -38,8 +37,7 @@ while.cond: ; preds = %entry, %for.cond26 if.then: ; preds = %while.cond %start = add nsw i32 %cell.0, 1 - %cond.v2 = call i1 @cond() - br i1 %cond.v2, label %for.cond11, label %for.cond26 + br i1 %cond.v, label %for.cond11, label %for.cond26 for.cond11: ; preds = %for.cond11, %if.then %i.1 = phi i32 [ %start, %if.then ], [ %step, %for.cond11 ] @@ -64,8 +62,7 @@ define void @phi_recurrence_step_first() { ; CHECK-NEXT: br i1 [[COND_V]], label [[IF_THEN:%.*]], label [[WHILE_END:%.*]] ; CHECK: if.then: ; CHECK-NEXT: [[START]] = add nuw nsw i32 [[CELL_0]], 1 -; CHECK-NEXT: [[COND_V2:%.*]] = call i1 @cond() -; CHECK-NEXT: br i1 [[COND_V2]], label [[FOR_COND11:%.*]], label [[FOR_COND26]] +; CHECK-NEXT: br i1 [[COND_V]], label [[FOR_COND11:%.*]], label [[FOR_COND26]] ; CHECK: for.cond11: ; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[STEP:%.*]], [[FOR_COND11]] ], [ [[START]], [[IF_THEN]] ] ; CHECK-NEXT: [[CMP13:%.*]] = icmp ult i32 [[I_1]], 100 @@ -86,8 +83,7 @@ while.cond: ; preds = %entry, %for.cond26 if.then: ; preds = %while.cond %start = add nsw i32 %cell.0, 1 - %cond.v2 = call i1 @cond() - br i1 %cond.v2, label %for.cond11, label %for.cond26 + br i1 %cond.v, label %for.cond11, label %for.cond26 for.cond11: ; preds = %for.cond11, %if.then %i.1 = phi i32 [ %step, %for.cond11 ], [ %start, %if.then] diff --git a/llvm/test/Transforms/InstCombine/phi.ll b/llvm/test/Transforms/InstCombine/phi.ll index ba29f4290a9fa4..673c8f6c9488d6 100644 --- a/llvm/test/Transforms/InstCombine/phi.ll +++ b/llvm/test/Transforms/InstCombine/phi.ll @@ -1543,7 +1543,7 @@ define i1 @phi_knownnonzero_eq_multiuse_oricmp(i32 %n, i32 %s, ptr %P, i32 %val) ; CHECK-NEXT: [[BOOL2:%.*]] = icmp eq i32 [[PHI]], 0 ; CHECK-NEXT: br label [[CLEANUP]] ; CHECK: cleanup: -; CHECK-NEXT: [[FINAL:%.*]] = phi i1 [ false, [[IF_END]] ], [ [[BOOL2]], [[NEXT]] ] +; CHECK-NEXT: [[FINAL:%.*]] = phi i1 [ [[CMP1]], [[IF_END]] ], [ [[BOOL2]], [[NEXT]] ] ; CHECK-NEXT: ret i1 [[FINAL]] ; entry: @@ -1581,13 +1581,13 @@ define i1 @phi_knownnonzero_ne_multiuse_oricmp_commuted(i32 %n, i32 %s, ptr %P, ; CHECK: if.end: ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 1, [[IF_THEN]] ], [ [[N]], [[ENTRY:%.*]] ] ; CHECK-NEXT: [[ORPHI:%.*]] = or i32 [[VAL:%.*]], [[PHI]] -; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i32 [[ORPHI]], 0 -; CHECK-NEXT: br i1 [[CMP1_NOT]], label [[CLEANUP:%.*]], label [[NEXT:%.*]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[ORPHI]], 0 +; CHECK-NEXT: br i1 [[CMP1]], label [[NEXT:%.*]], label [[CLEANUP:%.*]] ; CHECK: next: ; CHECK-NEXT: [[BOOL2:%.*]] = icmp ne i32 [[PHI]], 0 ; CHECK-NEXT: br label [[CLEANUP]] ; CHECK: cleanup: -; CHECK-NEXT: [[FINAL:%.*]] = phi i1 [ false, [[IF_END]] ], [ [[BOOL2]], [[NEXT]] ] +; CHECK-NEXT: [[FINAL:%.*]] = phi i1 [ [[CMP1]], [[IF_END]] ], [ [[BOOL2]], [[NEXT]] ] ; CHECK-NEXT: ret i1 [[FINAL]] ; entry: @@ -1634,7 +1634,7 @@ define i1 @phi_knownnonzero_eq_multiuse_andicmp(i32 %n, i32 %s, ptr %P, i32 %val ; CHECK-NEXT: [[BOOL2:%.*]] = icmp eq i32 [[PHI]], 0 ; CHECK-NEXT: br label [[CLEANUP]] ; CHECK: cleanup: -; CHECK-NEXT: [[FINAL:%.*]] = phi i1 [ false, [[IF_END]] ], [ [[BOOL2]], [[NEXT]] ] +; CHECK-NEXT: [[FINAL:%.*]] = phi i1 [ [[CMP1]], [[IF_END]] ], [ [[BOOL2]], [[NEXT]] ] ; CHECK-NEXT: ret i1 [[FINAL]] ; entry: @@ -1675,13 +1675,13 @@ define i1 @phi_knownnonzero_ne_multiuse_andicmp(i32 %n, i32 %s, ptr %P, i32 %val ; CHECK: if.end: ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[SEL]], [[IF_THEN]] ], [ [[N]], [[ENTRY:%.*]] ] ; CHECK-NEXT: [[ANDPHI:%.*]] = and i32 [[PHI]], [[VAL:%.*]] -; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i32 [[ANDPHI]], 0 -; CHECK-NEXT: br i1 [[CMP1_NOT]], label [[CLEANUP:%.*]], label [[NEXT:%.*]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[ANDPHI]], 0 +; CHECK-NEXT: br i1 [[CMP1]], label [[NEXT:%.*]], label [[CLEANUP:%.*]] ; CHECK: next: ; CHECK-NEXT: [[BOOL2:%.*]] = icmp ne i32 [[PHI]], 0 ; CHECK-NEXT: br label [[CLEANUP]] ; CHECK: cleanup: -; CHECK-NEXT: [[FINAL:%.*]] = phi i1 [ false, [[IF_END]] ], [ [[BOOL2]], [[NEXT]] ] +; CHECK-NEXT: [[FINAL:%.*]] = phi i1 [ [[CMP1]], [[IF_END]] ], [ [[BOOL2]], [[NEXT]] ] ; CHECK-NEXT: ret i1 [[FINAL]] ; entry: diff --git a/llvm/test/Transforms/InstCombine/pr44245.ll b/llvm/test/Transforms/InstCombine/pr44245.ll index 5625cc67b73420..ee5ae2edb42dae 100644 --- a/llvm/test/Transforms/InstCombine/pr44245.ll +++ b/llvm/test/Transforms/InstCombine/pr44245.ll @@ -3,7 +3,7 @@ ; This used to cause on infinite instcombine loop. -define void @test(i1 %c, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, i1 %c9, ptr %p) { +define void @test(i1 %c, ptr %p) { ; CHECK-LABEL: @test( ; CHECK-NEXT: bb16: ; CHECK-NEXT: br i1 [[C:%.*]], label [[BB17:%.*]], label [[BB24:%.*]] @@ -12,7 +12,7 @@ define void @test(i1 %c, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, ; CHECK-NEXT: store ptr [[I]], ptr [[P:%.*]], align 8 ; CHECK-NEXT: ret void ; CHECK: bb24: -; CHECK-NEXT: br i1 [[C2:%.*]], label [[BB44:%.*]], label [[BB49:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[BB44:%.*]], label [[BB49:%.*]] ; CHECK: bb44: ; CHECK-NEXT: [[TMP46:%.*]] = load ptr, ptr inttoptr (i64 16 to ptr), align 16 ; CHECK-NEXT: br label [[BB47]] @@ -20,37 +20,37 @@ define void @test(i1 %c, i1 %c2, i1 %c3, i1 %c4, i1 %c5, i1 %c6, i1 %c7, i1 %c8, ; CHECK-NEXT: [[DOTIN1]] = phi ptr [ [[DOTIN:%.*]], [[BB150:%.*]] ], [ [[TMP122:%.*]], [[BB119:%.*]] ], [ [[TMP103:%.*]], [[BB101:%.*]] ], [ [[TMP93:%.*]], [[BB91:%.*]] ], [ [[TMP83:%.*]], [[BB81:%.*]] ], [ [[TMP70:%.*]], [[BB67:%.*]] ], [ [[TMP58:%.*]], [[BB56:%.*]] ], [ [[TMP46]], [[BB44]] ] ; CHECK-NEXT: br label [[BB17]] ; CHECK: bb49: -; CHECK-NEXT: br i1 [[C3:%.*]], label [[BB56]], label [[BB59:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[BB56]], label [[BB59:%.*]] ; CHECK: bb56: ; CHECK-NEXT: [[TMP58]] = load ptr, ptr inttoptr (i64 16 to ptr), align 16 ; CHECK-NEXT: br label [[BB47]] ; CHECK: bb59: -; CHECK-NEXT: br i1 [[C4:%.*]], label [[BB67]], label [[BB71:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[BB67]], label [[BB71:%.*]] ; CHECK: bb67: ; CHECK-NEXT: [[TMP70]] = load ptr, ptr inttoptr (i64 16 to ptr), align 16 ; CHECK-NEXT: br label [[BB47]] ; CHECK: bb71: -; CHECK-NEXT: br i1 [[C5:%.*]], label [[BB81]], label [[BB84:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[BB81]], label [[BB84:%.*]] ; CHECK: bb81: ; CHECK-NEXT: [[TMP83]] = load ptr, ptr inttoptr (i64 16 to ptr), align 16 ; CHECK-NEXT: br label [[BB47]] ; CHECK: bb84: -; CHECK-NEXT: br i1 [[C6:%.*]], label [[BB91]], label [[BB94:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[BB91]], label [[BB94:%.*]] ; CHECK: bb91: ; CHECK-NEXT: [[TMP93]] = load ptr, ptr inttoptr (i64 16 to ptr), align 16 ; CHECK-NEXT: br label [[BB47]] ; CHECK: bb94: -; CHECK-NEXT: br i1 [[C7:%.*]], label [[BB101]], label [[BB104:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[BB101]], label [[BB104:%.*]] ; CHECK: bb101: ; CHECK-NEXT: [[TMP103]] = load ptr, ptr inttoptr (i64 16 to ptr), align 16 ; CHECK-NEXT: br label [[BB47]] ; CHECK: bb104: -; CHECK-NEXT: br i1 [[C8:%.*]], label [[BB119]], label [[BB123:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[BB119]], label [[BB123:%.*]] ; CHECK: bb119: ; CHECK-NEXT: [[TMP122]] = load ptr, ptr inttoptr (i64 16 to ptr), align 16 ; CHECK-NEXT: br label [[BB47]] ; CHECK: bb123: -; CHECK-NEXT: br i1 [[C9:%.*]], label [[BB147:%.*]], label [[BB152:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[BB147:%.*]], label [[BB152:%.*]] ; CHECK: bb147: ; CHECK-NEXT: [[TMP149:%.*]] = load ptr, ptr inttoptr (i64 16 to ptr), align 16 ; CHECK-NEXT: br label [[BB150]] @@ -70,7 +70,7 @@ bb17: ; preds = %bb47, %bb16 ret void bb24: ; preds = %bb16 - br i1 %c2, label %bb44, label %bb49 + br i1 %c, label %bb44, label %bb49 bb44: ; preds = %bb24 %tmp46 = load ptr, ptr inttoptr (i64 16 to ptr), align 16 @@ -81,49 +81,49 @@ bb47: ; preds = %bb150, %bb119, %bb1 br label %bb17 bb49: ; preds = %bb24 - br i1 %c3, label %bb56, label %bb59 + br i1 %c, label %bb56, label %bb59 bb56: ; preds = %bb49 %tmp58 = load ptr, ptr inttoptr (i64 16 to ptr), align 16 br label %bb47 bb59: ; preds = %bb49 - br i1 %c4, label %bb67, label %bb71 + br i1 %c, label %bb67, label %bb71 bb67: ; preds = %bb59 %tmp70 = load ptr, ptr inttoptr (i64 16 to ptr), align 16 br label %bb47 bb71: ; preds = %bb59 - br i1 %c5, label %bb81, label %bb84 + br i1 %c, label %bb81, label %bb84 bb81: ; preds = %bb71 %tmp83 = load ptr, ptr inttoptr (i64 16 to ptr), align 16 br label %bb47 bb84: ; preds = %bb71 - br i1 %c6, label %bb91, label %bb94 + br i1 %c, label %bb91, label %bb94 bb91: ; preds = %bb84 %tmp93 = load ptr, ptr inttoptr (i64 16 to ptr), align 16 br label %bb47 bb94: ; preds = %bb84 - br i1 %c7, label %bb101, label %bb104 + br i1 %c, label %bb101, label %bb104 bb101: ; preds = %bb94 %tmp103 = load ptr, ptr inttoptr (i64 16 to ptr), align 16 br label %bb47 bb104: ; preds = %bb94 - br i1 %c8, label %bb119, label %bb123 + br i1 %c, label %bb119, label %bb123 bb119: ; preds = %bb104 %tmp122 = load ptr, ptr inttoptr (i64 16 to ptr), align 16 br label %bb47 bb123: ; preds = %bb104 - br i1 %c9, label %bb147, label %bb152 + br i1 %c, label %bb147, label %bb152 bb147: ; preds = %bb123 %tmp149 = load ptr, ptr inttoptr (i64 16 to ptr), align 16 diff --git a/llvm/test/Transforms/InstCombine/sink-into-ncd.ll b/llvm/test/Transforms/InstCombine/sink-into-ncd.ll index 5fa692d3ae7288..464cc477a503c9 100644 --- a/llvm/test/Transforms/InstCombine/sink-into-ncd.ll +++ b/llvm/test/Transforms/InstCombine/sink-into-ncd.ll @@ -60,12 +60,12 @@ define i32 @test2(ptr %addr, i1 %c) { ; CHECK-NEXT: br label [[EXIT]] ; CHECK: right: ; CHECK-NEXT: [[Y:%.*]] = call i32 @use(ptr [[PTR]]) -; CHECK-NEXT: br i1 false, label [[EXIT]], label [[RIGHT_2:%.*]] +; CHECK-NEXT: br i1 [[C]], label [[EXIT]], label [[RIGHT_2:%.*]] ; CHECK: right.2: ; CHECK-NEXT: [[Z:%.*]] = call i32 @use(ptr [[PTR]]) ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: -; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[X]], [[LEFT]] ], [ poison, [[RIGHT]] ], [ [[Z]], [[RIGHT_2]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[X]], [[LEFT]] ], [ [[Y]], [[RIGHT]] ], [ [[Z]], [[RIGHT_2]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: ret i32 [[P]] ; entry: diff --git a/llvm/test/Transforms/InstCombine/sink_to_unreachable.ll b/llvm/test/Transforms/InstCombine/sink_to_unreachable.ll index 01510f8e9596b5..02ed22217854ea 100644 --- a/llvm/test/Transforms/InstCombine/sink_to_unreachable.ll +++ b/llvm/test/Transforms/InstCombine/sink_to_unreachable.ll @@ -42,8 +42,9 @@ define void @test_02(i32 %x, i32 %y) { ; CHECK-NEXT: [[C3:%.*]] = icmp sgt i32 [[X]], [[Y]] ; CHECK-NEXT: br i1 [[C3]], label [[EXIT]], label [[UNREACHED:%.*]] ; CHECK: unreached: -; CHECK-NEXT: [[C1:%.*]] = icmp ne i32 [[X]], [[Y]] -; CHECK-NEXT: [[COMPARATOR:%.*]] = zext i1 [[C1]] to i32 +; CHECK-NEXT: [[C1:%.*]] = icmp eq i32 [[X]], [[Y]] +; CHECK-NEXT: [[SIGNED:%.*]] = select i1 [[C2]], i32 -1, i32 1 +; CHECK-NEXT: [[COMPARATOR:%.*]] = select i1 [[C1]], i32 0, i32 [[SIGNED]] ; CHECK-NEXT: call void @use(i32 [[COMPARATOR]]) ; CHECK-NEXT: unreachable ; CHECK: exit: @@ -77,8 +78,9 @@ define i32 @test_03(i32 %x, i32 %y) { ; CHECK-NEXT: [[C3:%.*]] = icmp sgt i32 [[X]], [[Y]] ; CHECK-NEXT: br i1 [[C3]], label [[EXIT]], label [[UNREACHED:%.*]] ; CHECK: unreached: -; CHECK-NEXT: [[C1:%.*]] = icmp ne i32 [[X]], [[Y]] -; CHECK-NEXT: [[COMPARATOR:%.*]] = zext i1 [[C1]] to i32 +; CHECK-NEXT: [[C1:%.*]] = icmp eq i32 [[X]], [[Y]] +; CHECK-NEXT: [[SIGNED:%.*]] = select i1 [[C2]], i32 -1, i32 1 +; CHECK-NEXT: [[COMPARATOR:%.*]] = select i1 [[C1]], i32 0, i32 [[SIGNED]] ; CHECK-NEXT: ret i32 [[COMPARATOR]] ; CHECK: exit: ; CHECK-NEXT: ret i32 0 diff --git a/llvm/test/Transforms/InstCombine/zext-phi.ll b/llvm/test/Transforms/InstCombine/zext-phi.ll index a50e11c57c36ec..5a403eb1c1175e 100644 --- a/llvm/test/Transforms/InstCombine/zext-phi.ll +++ b/llvm/test/Transforms/InstCombine/zext-phi.ll @@ -1,4 +1,3 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s target datalayout = "e-m:e-i64:64-n8:16:32:64" @@ -7,21 +6,20 @@ target datalayout = "e-m:e-i64:64-n8:16:32:64" ; as a legal type because it is a fundamental type in IR. ; This means we should shrink the phi (sink the zexts). -define i64 @sink_i1_casts(i1 %cond1, i1 %cond2, i1 %cond) { -; CHECK-LABEL: define i64 @sink_i1_casts( -; CHECK-SAME: i1 [[COND1:%.*]], i1 [[COND2:%.*]], i1 [[COND:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*]]: -; CHECK-NEXT: br i1 [[COND]], label %[[IF:.*]], label %[[END:.*]] -; CHECK: [[IF]]: -; CHECK-NEXT: br label %[[END]] -; CHECK: [[END]]: -; CHECK-NEXT: [[PHI_IN1:%.*]] = phi i1 [ [[COND1]], %[[ENTRY]] ], [ [[COND2]], %[[IF]] ] -; CHECK-NEXT: [[PHI_IN:%.*]] = zext i1 [[PHI_IN1]] to i64 -; CHECK-NEXT: ret i64 [[PHI_IN]] +define i64 @sink_i1_casts(i1 %cond1, i1 %cond2) { +; CHECK-LABEL: @sink_i1_casts( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 %cond1, label %if, label %end +; CHECK: if: +; CHECK-NEXT: br label %end +; CHECK: end: +; CHECK-NEXT: [[PHI_IN:%.*]] = phi i1 [ %cond1, %entry ], [ %cond2, %if ] +; CHECK-NEXT: [[PHI:%.*]] = zext i1 [[PHI_IN]] to i64 +; CHECK-NEXT: ret i64 [[PHI]] ; entry: %z1 = zext i1 %cond1 to i64 - br i1 %cond, label %if, label %end + br i1 %cond1, label %if, label %end if: %z2 = zext i1 %cond2 to i64 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll b/llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll index d0decbff1a4625..c52227e1553756 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/uniform-args-call-variants.ll @@ -206,7 +206,7 @@ define void @test_uniform_not_invariant(ptr noalias %dst, ptr readonly %src, i64 ; INTERLEAVE-NEXT: br label [[VECTOR_BODY:%.*]] ; INTERLEAVE: vector.body: ; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE4:%.*]] ] -; INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY]], [[ENTRY]] ], [ true, [[PRED_STORE_CONTINUE4]] ] +; INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY]], [[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_STORE_CONTINUE4]] ] ; INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK2:%.*]] = phi i1 [ [[ACTIVE_LANE_MASK_ENTRY1]], [[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT5:%.*]], [[PRED_STORE_CONTINUE4]] ] ; INTERLEAVE-NEXT: br i1 [[ACTIVE_LANE_MASK]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] ; INTERLEAVE: pred.store.if: @@ -229,7 +229,7 @@ define void @test_uniform_not_invariant(ptr noalias %dst, ptr readonly %src, i64 ; INTERLEAVE: pred.store.continue4: ; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2 ; INTERLEAVE-NEXT: [[TMP10:%.*]] = or disjoint i64 [[INDEX]], 1 -; INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK_NEXT:%.*]] = icmp ult i64 [[INDEX]], [[TMP0]] +; INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = icmp ult i64 [[INDEX]], [[TMP0]] ; INTERLEAVE-NEXT: [[ACTIVE_LANE_MASK_NEXT5]] = icmp ult i64 [[TMP10]], [[TMP0]] ; INTERLEAVE-NEXT: br i1 [[ACTIVE_LANE_MASK_NEXT]], label [[VECTOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP4:![0-9]+]] ; INTERLEAVE: for.cond.cleanup: diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll index 04bed80b55de2c..335a850f1ec687 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll @@ -10,13 +10,18 @@ define i1 @test_order_1(ptr %this, ptr noalias %other, i1 %tobool9.not, i32 %cal ; CHECK-NEXT: entry: ; CHECK-NEXT: br i1 [[TOBOOL9_NOT]], label [[EXIT:%.*]], label [[FOR_COND_PREHEADER:%.*]] ; CHECK: for.cond.preheader: -; CHECK-NEXT: [[CMP40_NOT3:%.*]] = icmp sgt i32 [[CALL]], 0 +; CHECK-NEXT: [[CMP40_NOT3:%.*]] = icmp slt i32 [[CALL]], 1 ; CHECK-NEXT: br i1 [[CMP40_NOT3]], label [[FOR_COND41_PREHEADER_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: for.cond41.preheader.preheader: ; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[CALL]] to i64 ; CHECK-NEXT: br label [[FOR_COND41_PREHEADER:%.*]] +; CHECK: for.cond: +; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nsw i64 [[INDVARS_IV:%.*]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[INDVARS_IV_NEXT]], 4294967295 +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[TMP1]], 1 +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_COND41_PREHEADER]] ; CHECK: for.cond41.preheader: -; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP0]], [[FOR_COND_CLEANUP]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_COND:%.*]] ] +; CHECK-NEXT: [[INDVARS_IV]] = phi i64 [ [[TMP0]], [[FOR_COND41_PREHEADER_PREHEADER]] ], [ [[INDVARS_IV_NEXT]], [[FOR_COND:%.*]] ] ; CHECK-NEXT: [[CALL431:%.*]] = load volatile i32, ptr [[OTHER]], align 4 ; CHECK-NEXT: [[CMP442:%.*]] = icmp sgt i32 [[CALL431]], 0 ; CHECK-NEXT: br i1 [[CMP442]], label [[FOR_BODY45_LR_PH:%.*]], label [[FOR_COND]] @@ -31,11 +36,6 @@ define i1 @test_order_1(ptr %this, ptr noalias %other, i1 %tobool9.not, i32 %cal ; CHECK-NEXT: [[CALL43:%.*]] = load volatile i32, ptr [[OTHER]], align 4 ; CHECK-NEXT: [[CMP44:%.*]] = icmp sgt i32 [[CALL43]], 0 ; CHECK-NEXT: br i1 [[CMP44]], label [[FOR_BODY45]], label [[FOR_COND]] -; CHECK: for.inc57: -; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1 -; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[INDVARS_IV_NEXT]], 4294967295 -; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP1]], 1 -; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND41_PREHEADER_PREHEADER]], label [[FOR_COND41_PREHEADER]] ; CHECK: exit: ; CHECK-NEXT: ret i1 false ; diff --git a/llvm/test/Transforms/PhaseOrdering/branch-dom-cond.ll b/llvm/test/Transforms/PhaseOrdering/branch-dom-cond.ll deleted file mode 100644 index 904ea6c2d9e73b..00000000000000 --- a/llvm/test/Transforms/PhaseOrdering/branch-dom-cond.ll +++ /dev/null @@ -1,47 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -O3 -S < %s | FileCheck %s - -define void @growTables(ptr %p) { -; CHECK-LABEL: define void @growTables( -; CHECK-SAME: ptr [[P:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: [[ENTRY:.*]]: -; CHECK-NEXT: [[CALL:%.*]] = load volatile i32, ptr [[P]], align 4 -; CHECK-NEXT: [[CMP71:%.*]] = icmp sgt i32 [[CALL]], 0 -; CHECK-NEXT: br i1 [[CMP71]], label %[[FOR_BODY:.*]], label %[[COMMON_RET:.*]] -; CHECK: [[FOR_BODY]]: -; CHECK-NEXT: [[I_02:%.*]] = phi i32 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ] -; CHECK-NEXT: [[CALL9:%.*]] = load volatile ptr, ptr [[P]], align 8 -; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_02]], 1 -; CHECK-NEXT: [[CMP7:%.*]] = icmp slt i32 [[INC]], [[CALL]] -; CHECK-NEXT: br i1 [[CMP7]], label %[[FOR_BODY]], label %[[FOR_BODY12:.*]] -; CHECK: [[FOR_BODY12]]: -; CHECK-NEXT: [[CALL14:%.*]] = load volatile ptr, ptr [[P]], align 8 -; CHECK-NEXT: br label %[[COMMON_RET]] -; CHECK: [[COMMON_RET]]: -; CHECK-NEXT: ret void -; -entry: - %call = load volatile i32, ptr %p, align 4 - br label %for.cond - -for.cond: - %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ] - %cmp7 = icmp slt i32 %i.0, %call - br i1 %cmp7, label %for.body, label %for.end - -for.body: - %call9 = load volatile ptr, ptr %p, align 8 - %inc = add i32 %i.0, 1 - br label %for.cond - -for.end: - %cmp11 = icmp sgt i32 %call, 0 - br i1 %cmp11, label %for.body12, label %common.ret - -for.body12: - %call14 = load volatile ptr, ptr %p, align 8 - br label %common.ret - -common.ret: - ret void -} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
