================
@@ -877,6 +948,86 @@ Register
SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
int64_t Offset) const {
const SIInstrInfo *TII = ST.getInstrInfo();
+
+ switch (MI.getOpcode()) {
+ case AMDGPU::V_ADD_U32_e32:
+ case AMDGPU::V_ADD_CO_U32_e32: {
+ MachineOperand *FIOp = &MI.getOperand(2);
+ MachineOperand *ImmOp = &MI.getOperand(1);
+ if (!FIOp->isFI())
+ std::swap(FIOp, ImmOp);
+
+ if (!ImmOp->isImm()) {
+ assert(Offset == 0);
+ FIOp->ChangeToRegister(BaseReg, false);
+ TII->legalizeOperandsVOP2(MI.getMF()->getRegInfo(), MI);
+ return;
+ }
+
+ int64_t TotalOffset = ImmOp->getImm() + Offset;
+ if (TotalOffset == 0) {
+ MI.setDesc(TII->get(AMDGPU::COPY));
+ for (unsigned I = MI.getNumOperands() - 1; I != 1; --I)
+ MI.removeOperand(I);
+
+ MI.getOperand(1).ChangeToRegister(BaseReg, false);
+ return;
+ }
+
+ ImmOp->setImm(TotalOffset);
+
+ MachineBasicBlock *MBB = MI.getParent();
+ MachineFunction *MF = MBB->getParent();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+
+ // FIXME: materializeFrameBaseRegister does not know the register class of
+ // the uses of the frame index, and assumes SGPR for enableFlatScratch.
Emit
+ // a copy so we have a legal operand and hope the register coalescer can
+ // clean it up.
+ if (isSGPRReg(MRI, BaseReg)) {
+ Register BaseRegVGPR =
+ MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), BaseRegVGPR)
+ .addReg(BaseReg);
+ MI.getOperand(2).ChangeToRegister(BaseRegVGPR, false);
+ } else {
+ MI.getOperand(2).ChangeToRegister(BaseReg, false);
+ }
+ return;
+ }
+ case AMDGPU::V_ADD_U32_e64:
+ case AMDGPU::V_ADD_CO_U32_e64: {
+ int Src0Idx = MI.getNumExplicitDefs();
----------------
rampitec wrote:
Check that modifiers are clear?
https://github.com/llvm/llvm-project/pull/101692
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