https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/100787
Reorder for consistency, so the same types for v/s are together.
>From 794f20ecd9df0024481842bce8dd9e7d9e3684cb Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Fri, 26 Jul 2024 17:08:26 +0400
Subject: [PATCH] AMDGPU: Cleanup immediate selection patterns
Reorder for consistency, so the same types for v/s are together.
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 79 ++++++++++++------------
1 file changed, 41 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td
b/llvm/lib/Target/AMDGPU/SIInstructions.td
index d2101654d2acb..bcf778b31d276 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2138,19 +2138,26 @@ def : GCNPat <
/********** Immediate Patterns **********/
/********** ================== **********/
+// FIXME: Remove VGPRImm. Should be inferrable from register bank.
+
def : GCNPat <
(VGPRImm<(i32 imm)>:$imm),
(V_MOV_B32_e32 imm:$imm)
>;
def : GCNPat <
- (VGPRImm<(f32 fpimm)>:$imm),
- (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
+ (i32 imm:$imm),
+ (S_MOV_B32 imm:$imm)
>;
def : GCNPat <
- (i32 imm:$imm),
- (S_MOV_B32 imm:$imm)
+ (p5 frameindex:$fi),
+ (V_MOV_B32_e32 (p5 (frameindex_to_targetframeindex $fi)))
+>;
+
+def : GCNPat <
+ (p5 frameindex:$fi),
+ (S_MOV_B32 (p5 (frameindex_to_targetframeindex $fi)))
>;
def : GCNPat <
@@ -2168,40 +2175,34 @@ def : GCNPat <
(V_MOV_B32_e32 imm:$imm)
>;
-// FIXME: Workaround for ordering issue with peephole optimizer where
-// a register class copy interferes with immediate folding. Should
-// use s_mov_b32, which can be shrunk to s_movk_i32
def : GCNPat <
- (VGPRImm<(f16 fpimm)>:$imm),
- (V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm)))
+ (i16 imm:$imm),
+ (S_MOV_B32 imm:$imm)
>;
def : GCNPat <
- (VGPRImm<(bf16 fpimm)>:$imm),
- (V_MOV_B32_e32 (bf16 (bitcast_fpimm_to_i32 $imm)))
+ (VGPRImm<(f16 fpimm)>:$imm),
+ (V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm)))
>;
-// V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO can be used with any 64-bit
-// immediate and wil be expanded as needed, but we will only use these patterns
-// for values which can be encoded.
def : GCNPat <
- (VGPRImm<(i64 imm)>:$imm),
- (V_MOV_B64_PSEUDO imm:$imm)
+ (f16 fpimm:$imm),
+ (S_MOV_B32 (i32 (bitcast_fpimm_to_i32 $imm)))
>;
def : GCNPat <
- (VGPRImm<(f64 fpimm)>:$imm),
- (V_MOV_B64_PSEUDO (f64 (bitcast_fpimm_to_i64 $imm)))
+ (VGPRImm<(bf16 fpimm)>:$imm),
+ (V_MOV_B32_e32 (bf16 (bitcast_fpimm_to_i32 $imm)))
>;
def : GCNPat <
- (i64 imm:$imm),
- (S_MOV_B64_IMM_PSEUDO imm:$imm)
+ (bf16 fpimm:$imm),
+ (S_MOV_B32 (i32 (bitcast_fpimm_to_i32 $imm)))
>;
def : GCNPat <
- (f64 fpimm:$imm),
- (S_MOV_B64_IMM_PSEUDO (i64 (bitcast_fpimm_to_i64 fpimm:$imm)))
+ (VGPRImm<(f32 fpimm)>:$imm),
+ (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm)))
>;
def : GCNPat <
@@ -2210,31 +2211,38 @@ def : GCNPat <
>;
def : GCNPat <
- (f16 fpimm:$imm),
- (S_MOV_B32 (i32 (bitcast_fpimm_to_i32 $imm)))
+ (VGPRImm<(i64 imm)>:$imm),
+ (V_MOV_B64_PSEUDO imm:$imm)
>;
def : GCNPat <
- (bf16 fpimm:$imm),
- (S_MOV_B32 (i32 (bitcast_fpimm_to_i32 $imm)))
+ (i64 InlineImm64:$imm),
+ (S_MOV_B64 InlineImm64:$imm)
>;
def : GCNPat <
- (p5 frameindex:$fi),
- (V_MOV_B32_e32 (p5 (frameindex_to_targetframeindex $fi)))
+ (i64 imm:$imm),
+ (S_MOV_B64_IMM_PSEUDO imm:$imm)
>;
def : GCNPat <
- (p5 frameindex:$fi),
- (S_MOV_B32 (p5 (frameindex_to_targetframeindex $fi)))
+ (VGPRImm<(f64 fpimm)>:$imm),
+ (V_MOV_B64_PSEUDO (f64 (bitcast_fpimm_to_i64 $imm)))
>;
+// V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO can be used with any 64-bit
+// immediate and wil be expanded as needed, but we will only use these patterns
+// for values which can be encoded.
def : GCNPat <
- (i64 InlineImm64:$imm),
- (S_MOV_B64 InlineImm64:$imm)
+ (f64 InlineImmFP64:$imm),
+ (S_MOV_B64 (i64 (bitcast_fpimm_to_i64 $imm)))
+>;
+
+def : GCNPat <
+ (f64 fpimm:$imm),
+ (S_MOV_B64_IMM_PSEUDO (i64 (bitcast_fpimm_to_i64 fpimm:$imm)))
>;
-// Set to sign-extended 64-bit value (true = -1, false = 0)
// Set to sign-extended 64-bit value (true = -1, false = 0)
def : GCNPat <(i1 imm:$imm),
(S_MOV_B64 imm:$imm)> {
@@ -2246,11 +2254,6 @@ def : GCNPat <(i1 imm:$imm),
let WaveSizePredicate = isWave32;
}
-def : GCNPat <
- (f64 InlineImmFP64:$imm),
- (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineImmFP64:$imm)))
->;
-
/********** ================== **********/
/********** Intrinsic Patterns **********/
/********** ================== **********/
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