llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mc Author: None (llvmbot) <details> <summary>Changes</summary> Backport 1ebfc81a91194c000ac70b4ea53891cc956aa6eb Requested by: @<!-- -->wangpc-pp --- Full diff: https://github.com/llvm/llvm-project/pull/100306.diff 2 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (+4-4) - (modified) llvm/test/MC/RISCV/insn_c.s (+10) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index 9257ee5a09a8e..3f279b7a58ca6 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -764,9 +764,9 @@ def InsnCR : DirectiveInsnCR<(outs AnyReg:$rd), (ins uimm2_opcode:$opcode, uimm4:$funct4, AnyReg:$rs2), "$opcode, $funct4, $rd, $rs2">; -def InsnCI : DirectiveInsnCI<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode, - uimm3:$funct3, - simm6:$imm6), +def InsnCI : DirectiveInsnCI<(outs AnyReg:$rd), (ins uimm2_opcode:$opcode, + uimm3:$funct3, + simm6:$imm6), "$opcode, $funct3, $rd, $imm6">; def InsnCIW : DirectiveInsnCIW<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode, uimm3:$funct3, @@ -818,7 +818,7 @@ def : InstAlias<".insn_cr $opcode, $funct4, $rd, $rs2", (InsnCR AnyReg:$rd, uimm2_opcode:$opcode, uimm4:$funct4, AnyReg:$rs2)>; def : InstAlias<".insn_ci $opcode, $funct3, $rd, $imm6", - (InsnCI AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3, + (InsnCI AnyReg:$rd, uimm2_opcode:$opcode, uimm3:$funct3, simm6:$imm6)>; def : InstAlias<".insn_ciw $opcode, $funct3, $rd, $imm8", (InsnCIW AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3, diff --git a/llvm/test/MC/RISCV/insn_c.s b/llvm/test/MC/RISCV/insn_c.s index 19169e8b08c94..c63e8ab33aef9 100644 --- a/llvm/test/MC/RISCV/insn_c.s +++ b/llvm/test/MC/RISCV/insn_c.s @@ -31,6 +31,16 @@ target: # CHECK-OBJ: c.addi a0, 0xd .insn ci C1, 0, a0, 13 +# CHECK-ASM: .insn ci 1, 0, a6, 13 +# CHECK-ASM: encoding: [0x35,0x08] +# CHECK-OBJ: c.addi a6, 0xd +.insn ci 1, 0, a6, 13 + +# CHECK-ASM: .insn ci 1, 0, a6, 13 +# CHECK-ASM: encoding: [0x35,0x08] +# CHECK-OBJ: c.addi a6, 0xd +.insn ci C1, 0, a6, 13 + # CHECK-ASM: .insn ciw 0, 0, a0, 13 # CHECK-ASM: encoding: [0xa8,0x01] # CHECK-OBJ: c.addi4spn a0, sp, 0xc8 `````````` </details> https://github.com/llvm/llvm-project/pull/100306 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
