llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-amdgpu Author: AtariDreams (AtariDreams) <details> <summary>Changes</summary> As well as flipping the sense of the bit, GFX12 moved it from bit 0 to bit 1 in the encoded simm16 operand. (cherry picked from commit e0a763c490d8ef58dca867e0ef834978ccf8e17d) --- Full diff: https://github.com/llvm/llvm-project/pull/91034.diff 2 Files Affected: - (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+1-1) - (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll (+3-7) ``````````diff diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index ae5ef0541929b..5762efde73f02 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1786,7 +1786,7 @@ def : GCNPat< let SubtargetPredicate = isNotGFX12Plus in def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 0))>; let SubtargetPredicate = isGFX12Plus in - def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 1))>; + def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 2))>; // The first 10 bits of the mode register are the core FP mode on all // subtargets. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll index 08c77148f6ae1..433fefa434988 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll @@ -5,14 +5,10 @@ ; GCN-LABEL: {{^}}test_wait_event: ; GFX11: s_wait_event 0x0 -; GFX12: s_wait_event 0x1 +; GFX12: s_wait_event 0x2 -define amdgpu_ps void @test_wait_event() #0 { +define amdgpu_ps void @test_wait_event() { entry: - call void @llvm.amdgcn.s.wait.event.export.ready() #0 + call void @llvm.amdgcn.s.wait.event.export.ready() ret void } - -declare void @llvm.amdgcn.s.wait.event.export.ready() #0 - -attributes #0 = { nounwind } `````````` </details> https://github.com/llvm/llvm-project/pull/91034 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
