[llvm-branch-commits] [llvm] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

[Florian Mayer via llvm-branch-commits]

https://github.com/fmayer updated 
https://github.com/llvm/llvm-project/pull/84404

>From de96c71240c4c1021d8267cd8ccee4abc9299257 Mon Sep 17 00:00:00 2001
From: Florian Mayer <fma...@google.com>
Date: Thu, 14 Mar 2024 13:52:22 -0700
Subject: [PATCH] rename

Created using spr 1.3.4
---
 .../Transforms/Utils/MemoryTaggingSupport.h   |  2 +-
 .../Instrumentation/HWAddressSanitizer.cpp    | 30 +++++++++----------
 .../Transforms/Utils/MemoryTaggingSupport.cpp |  4 +--
 3 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h 
b/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
index cbbb8ff34a59e6..8c77e5efc96a3e 100644
--- a/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
+++ b/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
@@ -81,7 +81,7 @@ uint64_t getAllocaSizeInBytes(const AllocaInst &AI);
 void alignAndPadAlloca(memtag::AllocaInfo &Info, llvm::Align Align);
 
 Value *readRegister(IRBuilder<> &IRB, StringRef Name);
-Value *getSP(IRBuilder<> &IRB);
+Value *getFP(IRBuilder<> &IRB);
 Value *getPC(const Triple &TargetTriple, IRBuilder<> &IRB);
 
 } // namespace memtag
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp 
b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index 58361fc9d6dfae..0c15941dda8bb6 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -371,7 +371,7 @@ class HWAddressSanitizer {
   void instrumentGlobal(GlobalVariable *GV, uint8_t Tag);
   void instrumentGlobals();
 
-  Value *getCachedSP(IRBuilder<> &IRB);
+  Value *getCachedFP(IRBuilder<> &IRB);
   Value *getFrameRecordInfo(IRBuilder<> &IRB);
 
   void instrumentPersonalityFunctions();
@@ -446,7 +446,7 @@ class HWAddressSanitizer {
 
   Value *ShadowBase = nullptr;
   Value *StackBaseTag = nullptr;
-  Value *CachedSP = nullptr;
+  Value *CachedFP = nullptr;
   GlobalValue *ThreadPtrGlobal = nullptr;
 };
 
@@ -1166,10 +1166,10 @@ Value *HWAddressSanitizer::getStackBaseTag(IRBuilder<> 
&IRB) {
   // Extract some entropy from the stack pointer for the tags.
   // Take bits 20..28 (ASLR entropy) and xor with bits 0..8 (these differ
   // between functions).
-  Value *StackPointerLong = getCachedSP(IRB);
+  Value *FramePointerLong = getCachedFP(IRB);
   Value *StackTag =
-      applyTagMask(IRB, IRB.CreateXor(StackPointerLong,
-                                      IRB.CreateLShr(StackPointerLong, 20)));
+      applyTagMask(IRB, IRB.CreateXor(FramePointerLong,
+                                      IRB.CreateLShr(FramePointerLong, 20)));
   StackTag->setName("hwasan.stack.base.tag");
   return StackTag;
 }
@@ -1183,9 +1183,9 @@ Value *HWAddressSanitizer::getAllocaTag(IRBuilder<> &IRB, 
Value *StackTag,
 }
 
 Value *HWAddressSanitizer::getUARTag(IRBuilder<> &IRB) {
-  Value *StackPointerLong = getCachedSP(IRB);
+  Value *FramePointerLong = getCachedFP(IRB);
   Value *UARTag =
-      applyTagMask(IRB, IRB.CreateLShr(StackPointerLong, PointerTagShift));
+      applyTagMask(IRB, IRB.CreateLShr(FramePointerLong, PointerTagShift));
 
   UARTag->setName("hwasan.uar.tag");
   return UARTag;
@@ -1244,16 +1244,16 @@ Value 
*HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> &IRB, Type *Ty) {
   return nullptr;
 }
 
-Value *HWAddressSanitizer::getCachedSP(IRBuilder<> &IRB) {
-  if (!CachedSP)
-    CachedSP = memtag::getSP(IRB);
-  return CachedSP;
+Value *HWAddressSanitizer::getCachedFP(IRBuilder<> &IRB) {
+  if (!CachedFP)
+    CachedFP = memtag::getFP(IRB);
+  return CachedFP;
 }
 
 Value *HWAddressSanitizer::getFrameRecordInfo(IRBuilder<> &IRB) {
   // Prepare ring buffer data.
   Value *PC = memtag::getPC(TargetTriple, IRB);
-  Value *SP = getCachedSP(IRB);
+  Value *FP = getCachedFP(IRB);
 
   // Mix SP and PC.
   // Assumptions:
@@ -1261,8 +1261,8 @@ Value *HWAddressSanitizer::getFrameRecordInfo(IRBuilder<> 
&IRB) {
   // SP is 0xsssssssssssSSSS0  (4 lower bits are zero)
   // We only really need ~20 lower non-zero bits (SSSS), so we mix like this:
   //       0xSSSSPPPPPPPPPPPP
-  SP = IRB.CreateShl(SP, 44);
-  return IRB.CreateOr(PC, SP);
+  FP = IRB.CreateShl(FP, 44);
+  return IRB.CreateOr(PC, FP);
 }
 
 void HWAddressSanitizer::emitPrologue(IRBuilder<> &IRB, bool WithFrameRecord) {
@@ -1615,7 +1615,7 @@ void HWAddressSanitizer::sanitizeFunction(Function &F,
 
   ShadowBase = nullptr;
   StackBaseTag = nullptr;
-  CachedSP = nullptr;
+  CachedFP = nullptr;
 }
 
 void HWAddressSanitizer::instrumentGlobal(GlobalVariable *GV, uint8_t Tag) {
diff --git a/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp 
b/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
index 8b97a2745b1f8a..14cb965ff167f6 100644
--- a/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
+++ b/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
@@ -256,9 +256,7 @@ Value *getPC(const Triple &TargetTriple, IRBuilder<> &IRB) {
                             IRB.getIntPtrTy(M->getDataLayout()));
 }
 
-Value *getSP(IRBuilder<> &IRB) {
-  // FIXME: use addressofreturnaddress (but implement it in aarch64 backend
-  // first).
+Value *getFP(IRBuilder<> &IRB) {
   Function *F = IRB.GetInsertBlock()->getParent();
   Module *M = F->getParent();
   auto *GetStackPointerFn = Intrinsic::getDeclaration(

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