[llvm-branch-commits] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN, SMAX, UMIN, UMAX} for odd-sized vectors (PR #81831)

[Dhruv Chawla via llvm-branch-commits]

https://github.com/dc03-work closed 
https://github.com/llvm/llvm-project/pull/81831
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