Author: Paul Walker Date: 2023-11-03T12:10:48Z New Revision: 51485019fb34a48dc6226bfa42d7449091e3f03d
URL: https://github.com/llvm/llvm-project/commit/51485019fb34a48dc6226bfa42d7449091e3f03d DIFF: https://github.com/llvm/llvm-project/commit/51485019fb34a48dc6226bfa42d7449091e3f03d.diff LOG: [NFC][LLVM][SVE] Refactor predicate register ASM constraint parsing to use std::optional. Added: Modified: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 291f0c8c5d991c6..94901c2d1a65688 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -10163,14 +10163,15 @@ const char *AArch64TargetLowering::LowerXConstraint(EVT ConstraintVT) const { return "r"; } -enum PredicateConstraint { Uph, Upl, Upa, Invalid }; +enum class PredicateConstraint { Uph, Upl, Upa }; -static PredicateConstraint parsePredicateConstraint(StringRef Constraint) { - return StringSwitch<PredicateConstraint>(Constraint) +static std::optional<PredicateConstraint> +parsePredicateConstraint(StringRef Constraint) { + return StringSwitch<std::optional<PredicateConstraint>>(Constraint) .Case("Uph", PredicateConstraint::Uph) .Case("Upl", PredicateConstraint::Upl) .Case("Upa", PredicateConstraint::Upa) - .Default(PredicateConstraint::Invalid); + .Default(std::nullopt); } static const TargetRegisterClass * @@ -10180,8 +10181,6 @@ getPredicateRegisterClass(PredicateConstraint Constraint, EVT VT) { return nullptr; switch (Constraint) { - default: - return nullptr; case PredicateConstraint::Uph: return VT == MVT::aarch64svcount ? &AArch64::PNR_p8to15RegClass : &AArch64::PPR_p8to15RegClass; @@ -10192,6 +10191,8 @@ getPredicateRegisterClass(PredicateConstraint Constraint, EVT VT) { return VT == MVT::aarch64svcount ? &AArch64::PNRRegClass : &AArch64::PPRRegClass; } + + llvm_unreachable("Missing PredicateConstraint!"); } // The set of cc code supported is from @@ -10289,9 +10290,8 @@ AArch64TargetLowering::getConstraintType(StringRef Constraint) const { case 'S': // A symbolic address return C_Other; } - } else if (parsePredicateConstraint(Constraint) != - PredicateConstraint::Invalid) - return C_RegisterClass; + } else if (parsePredicateConstraint(Constraint)) + return C_RegisterClass; else if (parseConstraintCode(Constraint) != AArch64CC::Invalid) return C_Other; return TargetLowering::getConstraintType(Constraint); @@ -10325,7 +10325,7 @@ AArch64TargetLowering::getSingleConstraintMatchWeight( weight = CW_Constant; break; case 'U': - if (parsePredicateConstraint(constraint) != PredicateConstraint::Invalid) + if (parsePredicateConstraint(constraint)) weight = CW_Register; break; } @@ -10382,9 +10382,9 @@ AArch64TargetLowering::getRegForInlineAsmConstraint( break; } } else { - PredicateConstraint PC = parsePredicateConstraint(Constraint); - if (const TargetRegisterClass *RegClass = getPredicateRegisterClass(PC, VT)) - return std::make_pair(0U, RegClass); + if (const auto PC = parsePredicateConstraint(Constraint)) + if (const auto *RegClass = getPredicateRegisterClass(*PC, VT)) + return std::make_pair(0U, RegClass); } if (StringRef("{cc}").equals_insensitive(Constraint) || parseConstraintCode(Constraint) != AArch64CC::Invalid) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
