Author: Craig Topper Date: 2022-04-05T21:56:05-07:00 New Revision: e9b26b5b2a709156f6d68927fa01c0a0540ea625
URL: https://github.com/llvm/llvm-project/commit/e9b26b5b2a709156f6d68927fa01c0a0540ea625 DIFF: https://github.com/llvm/llvm-project/commit/e9b26b5b2a709156f6d68927fa01c0a0540ea625.diff LOG: [RISCV] Add test case for miscompile caused by treating ANY_EXTEND of constants as SIGN_EXTEND. The code that inserts AssertZExt based on predecessor information assumes constants are zero extended for phi incoming values this allows AssertZExt to be created in blocks consuming a Phi. SelectionDAG::getNode treats any_extend of i32 constants as sext for RISCV. The code that creates phi incoming values in the predecessors creates an any_extend for the constants which then gets treated as a sext by getNode. This makes the AssertZExt incorrect and can cause zexts to be incorrectly removed. This bug was introduced by D105918 Differential Revision: https://reviews.llvm.org/D122052 (cherry picked from commit 268371cf7b9f6fd3b9320564f1abd3615eecd2e8) Added: Modified: llvm/test/CodeGen/RISCV/aext-to-sext.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/RISCV/aext-to-sext.ll b/llvm/test/CodeGen/RISCV/aext-to-sext.ll index df90981508a9b..0ffdf085109ec 100644 --- a/llvm/test/CodeGen/RISCV/aext-to-sext.ll +++ b/llvm/test/CodeGen/RISCV/aext-to-sext.ll @@ -75,3 +75,36 @@ bb: bar: ret i32 %b } + +; The code that inserts AssertZExt based on predecessor information assumes +; constants are zero extended for phi incoming values so an AssertZExt is +; created in 'merge' allowing the zext to be removed. +; SelectionDAG::getNode treats any_extend of i32 constants as sext for RISCV. +; The code that creates phi incoming values in the predecessors creates an +; any_extend for the constants which then gets treated as a sext by getNode. +; This means the zext was not safe to remove. +define i64 @miscompile(i32 %c) { +; RV64I-LABEL: miscompile: +; RV64I: # %bb.0: +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: li a0, -1 +; RV64I-NEXT: beqz a1, .LBB2_2 +; RV64I-NEXT: # %bb.1: # %merge +; RV64I-NEXT: ret +; RV64I-NEXT: .LBB2_2: # %iffalse +; RV64I-NEXT: li a0, -2 +; RV64I-NEXT: ret + %a = icmp ne i32 %c, 0 + br i1 %a, label %iftrue, label %iffalse + +iftrue: + br label %merge + +iffalse: + br label %merge + +merge: + %b = phi i32 [-1, %iftrue], [-2, %iffalse] + %d = zext i32 %b to i64 + ret i64 %d +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
