Author: Alex Bradbury Date: 2022-02-28T10:52:32-08:00 New Revision: ee0ae47691d30802ae1eeb056d53886800d3c2fa
URL: https://github.com/llvm/llvm-project/commit/ee0ae47691d30802ae1eeb056d53886800d3c2fa DIFF: https://github.com/llvm/llvm-project/commit/ee0ae47691d30802ae1eeb056d53886800d3c2fa.diff LOG: [RISCV] Avoid infinite loop between DAGCombiner::visitMUL and RISCVISelLowering::transformAddImmMulImm See https://github.com/llvm/llvm-project/issues/53831 for a full discussion. The basic issue is that DAGCombiner::visitMUL and RISCVISelLowering;:transformAddImmMullImm get stuck in a loop, as the current checks in transformAddImmMulImm aren't sufficient to avoid all cases where DAGCombiner::isMulAddWithConstProfitable might trigger a transformation. This patch makes transformAddImmMulImm bail out if C0 (the constant used for multiplication) has more than one use. Differential Revision: https://reviews.llvm.org/D120332 (cherry picked from commit c5bcfb983e47167a8a1826c1a64d7aa1849add06) Added: Modified: llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/test/CodeGen/RISCV/addimm-mulimm.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 2fe491ad5ea42..7f5555b9b7a85 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -7203,6 +7203,11 @@ static SDValue transformAddImmMulImm(SDNode *N, SelectionDAG &DAG, auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)); if (!N0C || !N1C) return SDValue(); + // If N0C has multiple uses it's possible one of the cases in + // DAGCombiner::isMulAddWithConstProfitable will be true, which would result + // in an infinite loop. + if (!N0C->hasOneUse()) + return SDValue(); int64_t C0 = N0C->getSExtValue(); int64_t C1 = N1C->getSExtValue(); int64_t CA, CB; diff --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll index 4706f3904701d..adf0b98742e1b 100644 --- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll +++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll @@ -872,3 +872,16 @@ define i64 @mulneg3000_sub8990_c(i64 %x) { %tmp1 = add i64 %tmp0, -8990 ret i64 %tmp1 } + +; This test case previously caused an infinite loop between transformations +; performed in RISCVISelLowering;:transformAddImmMulImm and +; DAGCombiner::visitMUL. +define i1 @pr53831(i32 %x) { + %tmp0 = add i32 %x, 1 + %tmp1 = mul i32 %tmp0, 24 + %tmp2 = add i32 %tmp1, 1 + %tmp3 = mul i32 %x, 24 + %tmp4 = add i32 %tmp3, 2048 + %tmp5 = icmp eq i32 %tmp4, %tmp2 + ret i1 %tmp5 +} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
