Author: Bradley Smith Date: 2022-02-22T11:14:30-08:00 New Revision: 03d9a4094763b33be4e1ae908f5ff9a1787cf8d3
URL: https://github.com/llvm/llvm-project/commit/03d9a4094763b33be4e1ae908f5ff9a1787cf8d3 DIFF: https://github.com/llvm/llvm-project/commit/03d9a4094763b33be4e1ae908f5ff9a1787cf8d3.diff LOG: [AArch64][SVE] Fix selection failure during lowering of shuffle_vector The lowering code for shuffle_vector has a code path that looks through extract_subvector, this code path did not properly account for the potential presense of larger than Neon vector types and could produce unselectable DAG nodes. Differential Revision: https://reviews.llvm.org/D119252 (cherry picked from commit 98936aee7d41f9ae60dd06558fbbb1e6a4a89e17) Added: Modified: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index aa2dca3eda4b..ac5e51e47ddf 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9733,6 +9733,10 @@ static SDValue constructDup(SDValue V, int Lane, SDLoc dl, EVT VT, if (ExtIdxInBits % CastedEltBitWidth != 0) return false; + // Can't handle cases where vector size is not 128-bit + if (!Extract.getOperand(0).getValueType().is128BitVector()) + return false; + // Update the lane value by offsetting with the scaled extract index. LaneC += ExtIdxInBits / CastedEltBitWidth; diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll index 4e53128e1346..98f4077ef85d 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll @@ -1,4 +1,4 @@ -; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s +; RUN: llc < %s | FileCheck %s target triple = "aarch64-unknown-linux-gnu" @@ -14,4 +14,22 @@ define void @hang_when_merging_stores_after_legalisation(<8 x i32>* %a, <2 x i32 ret void } -attributes #0 = { nounwind "target-features"="+sve" } +; Ensure we don't crash when trying to lower a shuffle via and extract +define void @crash_when_lowering_extract_shuffle(<32 x i32>* %dst, i1 %cond) #0 { +; CHECK-LABEL: crash_when_lowering_extract_shuffle: +; CHECK: ld1w { z3.s }, p0/z, [x0] +; CHECK: st1w { z3.s }, p0, [x0] + %broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer + br i1 %cond, label %exit, label %vector.body + +vector.body: + %1 = load <32 x i32>, <32 x i32>* %dst, align 16 + %predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1 + store <32 x i32> %predphi, <32 x i32>* %dst, align 16 + br label %exit + +exit: + ret void +} + +attributes #0 = { vscale_range(2,2) "target-features"="+sve" } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
