Author: Craig Topper Date: 2022-02-21T11:20:52-08:00 New Revision: 908c1bae6e7fa2339e8b9b7856d849f20e98f653
URL: https://github.com/llvm/llvm-project/commit/908c1bae6e7fa2339e8b9b7856d849f20e98f653 DIFF: https://github.com/llvm/llvm-project/commit/908c1bae6e7fa2339e8b9b7856d849f20e98f653.diff LOG: [RISCV] Fix incorrect extend type in vwmulsu combine. While matching widening multiply, if we matched an extend from i8->i32, i16->i64 or i8->i64, we need to reintroduce a narrower extend. If we're matching a vwmulsu we need to use a sext for op0 and a zext for op1. This bug exists in LLVM 14 and will need to be backported. Differential Revision: https://reviews.llvm.org/D119618 (cherry picked from commit 478c237e21b2c3a83e46f26fcbeb3876682f9b14) Added: Modified: llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 97d24c8e9c0b..2fe491ad5ea4 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -7443,6 +7443,8 @@ static SDValue combineMUL_VLToVWMUL_VL(SDNode *N, SelectionDAG &DAG, unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; if (Op0.getValueType() != NarrowVT) Op0 = DAG.getNode(ExtOpc, DL, NarrowVT, Op0, Mask, VL); + // vwmulsu requires second operand to be zero extended. + ExtOpc = IsVWMULSU ? RISCVISD::VZEXT_VL : ExtOpc; if (Op1.getValueType() != NarrowVT) Op1 = DAG.getNode(ExtOpc, DL, NarrowVT, Op1, Mask, VL); diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll index 6c204b24ae2b..ffe4c5613090 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll @@ -375,7 +375,7 @@ define <2 x i32> @vwmulsu_v2i32_v2i8(<2 x i8>* %x, <2 x i8>* %y) { ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v9, (a1) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu -; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vsext.vf2 v11, v9 ; CHECK-NEXT: vwmulsu.vv v8, v11, v10 ; CHECK-NEXT: ret @@ -394,7 +394,7 @@ define <4 x i32> @vwmulsu_v4i32_v4i8_v4i16(<4 x i8>* %x, <4 x i16>* %y) { ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu -; CHECK-NEXT: vsext.vf2 v10, v8 +; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vwmulsu.vv v8, v9, v10 ; CHECK-NEXT: ret %a = load <4 x i8>, <4 x i8>* %x _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
