Author: Kai Nacke Date: 2022-02-11T11:52:25-05:00 New Revision: ff99f3a5c0b36d49f4be1b990cc7509e897d48c7
URL: https://github.com/llvm/llvm-project/commit/ff99f3a5c0b36d49f4be1b990cc7509e897d48c7 DIFF: https://github.com/llvm/llvm-project/commit/ff99f3a5c0b36d49f4be1b990cc7509e897d48c7.diff LOG: [SystemZ/z/OS] Add alias for XPLINK return The XPLINK return `b 2(7)` has size 4 bytes, while the Linux return `br 7` only has size 2 bytes. Thus a new alias is required to have correct instruction byte count. It also fixes the conditional return code. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D119437 Added: Modified: llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.td llvm/lib/Target/SystemZ/SystemZScheduleZ13.td llvm/lib/Target/SystemZ/SystemZScheduleZ14.td llvm/lib/Target/SystemZ/SystemZScheduleZ15.td llvm/lib/Target/SystemZ/SystemZScheduleZ196.td llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td Removed: ################################################################################ diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index e01adcce04ab1..84b337685c148 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -126,15 +126,18 @@ static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) { void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) { SystemZMCInstLower Lower(MF->getContext(), *this); - const SystemZSubtarget *Subtarget = &MF->getSubtarget<SystemZSubtarget>(); MCInst LoweredMI; switch (MI->getOpcode()) { case SystemZ::Return: - if (Subtarget->isTargetXPLINK64()) - LoweredMI = - MCInstBuilder(SystemZ::B).addReg(SystemZ::R7D).addImm(2).addReg(0); - else - LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D); + LoweredMI = MCInstBuilder(SystemZ::BR) + .addReg(SystemZ::R14D); + break; + + case SystemZ::Return_XPLINK: + LoweredMI = MCInstBuilder(SystemZ::B) + .addReg(SystemZ::R7D) + .addImm(2) + .addReg(0); break; case SystemZ::CondReturn: @@ -144,6 +147,15 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) { .addReg(SystemZ::R14D); break; + case SystemZ::CondReturn_XPLINK: + LoweredMI = MCInstBuilder(SystemZ::BC) + .addImm(MI->getOperand(0).getImm()) + .addImm(MI->getOperand(1).getImm()) + .addReg(SystemZ::R7D) + .addImm(2) + .addReg(0); + break; + case SystemZ::CRBReturn: LoweredMI = MCInstBuilder(SystemZ::CRB) .addReg(MI->getOperand(0).getReg()) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 4b6aa60f5d55a..aca1c27f97954 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -674,6 +674,7 @@ bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const { unsigned Opcode = MI.getOpcode(); if (Opcode == SystemZ::Return || + Opcode == SystemZ::Return_XPLINK || Opcode == SystemZ::Trap || Opcode == SystemZ::CallJG || Opcode == SystemZ::CallBR) @@ -731,11 +732,13 @@ bool SystemZInstrInfo::PredicateInstruction( .addReg(SystemZ::CC, RegState::Implicit); return true; } - if (Opcode == SystemZ::Return) { - MI.setDesc(get(SystemZ::CondReturn)); + if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) { + MI.setDesc(get(Opcode == SystemZ::Return ? SystemZ::CondReturn + : SystemZ::CondReturn_XPLINK)); MachineInstrBuilder(*MI.getParent()->getParent(), MI) - .addImm(CCValid).addImm(CCMask) - .addReg(SystemZ::CC, RegState::Implicit); + .addImm(CCValid) + .addImm(CCMask) + .addReg(SystemZ::CC, RegState::Implicit); return true; } if (Opcode == SystemZ::CallJG) { diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 84f1e0fb428c3..c47731b26e95d 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -336,13 +336,25 @@ let isCall = 1, isTerminator = 1, isReturn = 1 in { def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; } -// A return instruction (br %r14) for ELF and (b 2 %r7) for XPLink. -let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in - def Return : Alias<2, (outs), (ins), [(z_retflag)]>; +let Predicates = [IsTargetXPLINK64] in { + // A return instruction (b 2(%r7)). + let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in + def Return_XPLINK : Alias<4, (outs), (ins), [(z_retflag)]>; + + // A conditional return instruction (bc <cond>, 2(%r7)). + let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in + def CondReturn_XPLINK : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; +} -// A conditional return instruction (bcr <cond>, %r14). -let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in - def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; +let Predicates = [IsTargetELF] in { + // A return instruction (br %r14). + let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in + def Return : Alias<2, (outs), (ins), [(z_retflag)]>; + + // A conditional return instruction (bcr <cond>, %r14). + let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in + def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; +} // Fused compare and conditional returns. let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index f4777b0097f1e..ac92501470155 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -172,8 +172,8 @@ def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "(Call)?BAS(R)?(_XPLINK6 def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; // Return -def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>; -def : InstRW<[WLat1, FXb, NormalGr], (instregex "CondReturn$")>; +def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return(_XPLINK)?$")>; +def : InstRW<[WLat1, FXb, NormalGr], (instregex "CondReturn(_XPLINK)?$")>; //===----------------------------------------------------------------------===// // Move instructions diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td index f74c0d594482a..683b66a6f1edc 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -173,8 +173,8 @@ def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "(Call)?BAS(R)?(_XPLINK6 def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; // Return -def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>; -def : InstRW<[WLat1, FXb, NormalGr], (instregex "CondReturn$")>; +def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return(_XPLINK)?$")>; +def : InstRW<[WLat1, FXb, NormalGr], (instregex "CondReturn(_XPLINK)?$")>; //===----------------------------------------------------------------------===// // Move instructions diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td index d17e58fc63188..2ebdf508f22ba 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td @@ -173,8 +173,8 @@ def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "(Call)?BAS(R)?(_XPLINK6 def : InstRW<[WLat1, FXa2, FXb, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; // Return -def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return$")>; -def : InstRW<[WLat1, FXb, NormalGr], (instregex "CondReturn$")>; +def : InstRW<[WLat1, FXb, EndGroup], (instregex "Return(_XPLINK)?$")>; +def : InstRW<[WLat1, FXb, NormalGr], (instregex "CondReturn(_XPLINK)?$")>; //===----------------------------------------------------------------------===// // Move instructions diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index 0f01a4291cf78..51c87c2380c0e 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -151,8 +151,8 @@ def : InstRW<[WLat1, LSU, FXU2, GroupAlone], (instregex "(Call)?BAS(R)?(_XPLINK6 def : InstRW<[WLat1, LSU, FXU2, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; // Return -def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return$")>; -def : InstRW<[WLat1, LSU, EndGroup], (instregex "CondReturn$")>; +def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return(_XPLINK)?$")>; +def : InstRW<[WLat1, LSU, EndGroup], (instregex "CondReturn(_XPLINK)?$")>; //===----------------------------------------------------------------------===// // Move instructions diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index 096a95a82ec80..8f2379ce052af 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -156,8 +156,8 @@ def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BAS(R)?(_XPLINK6 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; // Return -def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return$")>; -def : InstRW<[WLat1, LSU, NormalGr], (instregex "CondReturn$")>; +def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return(_XPLINK)?$")>; +def : InstRW<[WLat1, LSU, NormalGr], (instregex "CondReturn(_XPLINK)?$")>; //===----------------------------------------------------------------------===// // Move instructions _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
