Author: Tom Stellard Date: 2021-04-29T23:26:25-07:00 New Revision: 25dd67ef882c327f9b6a3082cab6c33c9ff52d42
URL: https://github.com/llvm/llvm-project/commit/25dd67ef882c327f9b6a3082cab6c33c9ff52d42 DIFF: https://github.com/llvm/llvm-project/commit/25dd67ef882c327f9b6a3082cab6c33c9ff52d42.diff LOG: [X86][AVX] foldShuffleOfHorizOp - don't attempt to handle 256-bit X86ISD::VBROADCAST (PR49971) NOTE: This is for the 12.x release branch ONLY Minimal patch to avoid the issue encountered in PR49971 (it's already been dealt with in trunk through a larger refactor that can't be easily merged). Bail for non-128-bit vector broadcasts of (F)HADD/SUB ops - the existing logic doesn't correctly deal with the fact that the broadcast will splat across the 128-bit lanes. Reviewed By: spatel, wristow Differential Revision: https://reviews.llvm.org/D101104 Added: Modified: llvm/lib/Target/X86/X86ISelLowering.cpp llvm/test/CodeGen/X86/horizontal-shuffle-3.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6b816c710f987..1e2407c7e7f6b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -37889,6 +37889,8 @@ static SDValue foldShuffleOfHorizOp(SDNode *N, SelectionDAG &DAG) { // replicating low and high halves (and without changing the type/length of // the vector), we don't need the shuffle. if (Opcode == X86ISD::MOVDDUP || Opcode == X86ISD::VBROADCAST) { + if (Opcode == X86ISD::VBROADCAST && !VT.is128BitVector()) + return SDValue(); if (HOp.getScalarValueSizeInBits() == 64 && HOp.getValueType() == VT) { // movddup (hadd X, X) --> hadd X, X // broadcast (extract_vec_elt (hadd X, X), 0) --> hadd X, X diff --git a/llvm/test/CodeGen/X86/horizontal-shuffle-3.ll b/llvm/test/CodeGen/X86/horizontal-shuffle-3.ll index 424ecf352e972..297070ad2bb60 100644 --- a/llvm/test/CodeGen/X86/horizontal-shuffle-3.ll +++ b/llvm/test/CodeGen/X86/horizontal-shuffle-3.ll @@ -98,6 +98,17 @@ define <8 x i32> @test_unpackhi_hsub_v8i32(<8 x i32> %0, <8 x i32> %1, <8 x i32> ret <8 x i32> %7 } +define <4 x double> @PR49971(<4 x double> %0) { +; CHECK-LABEL: PR49971: +; CHECK: ## %bb.0: +; CHECK-NEXT: vhaddpd %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %2 = tail call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %0, <4 x double> %0) + %3 = shufflevector <4 x double> %2, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + ret <4 x double> %3 +} + declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
