Author: ShihPo Hung Date: 2021-03-30T14:30:15-07:00 New Revision: 9ae9ab1ca34384e07b751c16645e22a0b953b08b
URL: https://github.com/llvm/llvm-project/commit/9ae9ab1ca34384e07b751c16645e22a0b953b08b DIFF: https://github.com/llvm/llvm-project/commit/9ae9ab1ca34384e07b751c16645e22a0b953b08b.diff LOG: [RISCV][MC] Fix nf encoding for vector ld/st whole register The three bit nf is one less than the number of NFIELDS, so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R. Differential revision: https://reviews.llvm.org/D98185 (cherry picked from commit rG5cdb2e98608bf57c216ee7067e8a12d070c9e2bd) Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoV.td llvm/test/MC/RISCV/rvv/aliases.s llvm/test/MC/RISCV/rvv/load.s llvm/test/MC/RISCV/rvv/store.s Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 86fbc73d81d51..b3fc76aee1614 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -504,19 +504,19 @@ def VSOXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsoxei16.v">; def VSOXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsoxei32.v">; def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">; -defm VL1R : VWholeLoad<1, "vl1r">; -defm VL2R : VWholeLoad<2, "vl2r">; -defm VL4R : VWholeLoad<4, "vl4r">; -defm VL8R : VWholeLoad<8, "vl8r">; +defm VL1R : VWholeLoad<0, "vl1r">; +defm VL2R : VWholeLoad<1, "vl2r">; +defm VL4R : VWholeLoad<3, "vl4r">; +defm VL8R : VWholeLoad<7, "vl8r">; def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VR:$vd, GPR:$rs1)>; -def VS1R_V : VWholeStore<1, "vs1r.v">; -def VS2R_V : VWholeStore<2, "vs2r.v">; -def VS4R_V : VWholeStore<4, "vs4r.v">; -def VS8R_V : VWholeStore<8, "vs8r.v">; +def VS1R_V : VWholeStore<0, "vs1r.v">; +def VS2R_V : VWholeStore<1, "vs2r.v">; +def VS4R_V : VWholeStore<3, "vs4r.v">; +def VS8R_V : VWholeStore<7, "vs8r.v">; // Vector Single-Width Integer Add and Subtract defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; diff --git a/llvm/test/MC/RISCV/rvv/aliases.s b/llvm/test/MC/RISCV/rvv/aliases.s index 2e5120c91e451..ebe9e79399a69 100644 --- a/llvm/test/MC/RISCV/rvv/aliases.s +++ b/llvm/test/MC/RISCV/rvv/aliases.s @@ -54,17 +54,17 @@ vmset.m v0 # ALIAS: vmnot.m v0, v1 # encoding: [0x57,0xa0,0x10,0x76] # NO-ALIAS: vmnand.mm v0, v1, v1 # encoding: [0x57,0xa0,0x10,0x76] vmnot.m v0, v1 -# ALIAS: vl1r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x22] -# NO-ALIAS: vl1re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x22] +# ALIAS: vl1r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x02] +# NO-ALIAS: vl1re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x02] vl1r.v v0, (a0) -# ALIAS: vl2r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x42] -# NO-ALIAS: vl2re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x42] +# ALIAS: vl2r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x22] +# NO-ALIAS: vl2re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x22] vl2r.v v0, (a0) -# ALIAS: vl4r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x82] -# NO-ALIAS: vl4re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x82] +# ALIAS: vl4r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x62] +# NO-ALIAS: vl4re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x62] vl4r.v v0, (a0) -# ALIAS: vl8r.v v0, (a0) # encoding: [0x07,0x00,0x85,0x02] -# NO-ALIAS: vl8re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0x02] +# ALIAS: vl8r.v v0, (a0) # encoding: [0x07,0x00,0x85,0xe2] +# NO-ALIAS: vl8re8.v v0, (a0) # encoding: [0x07,0x00,0x85,0xe2] vl8r.v v0, (a0) # ALIAS: vneg.v v2, v1, v0.t # encoding: [0x57,0x41,0x10,0x0c] # NO-ALIAS: vrsub.vx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0x0c] diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s index 3d0dbb15c36ec..45a3881cb60d1 100644 --- a/llvm/test/MC/RISCV/rvv/load.s +++ b/llvm/test/MC/RISCV/rvv/load.s @@ -256,96 +256,96 @@ vloxei64.v v8, (a0), v4 vl1re8.v v8, (a0) # CHECK-INST: vl1re8.v v8, (a0) -# CHECK-ENCODING: [0x07,0x04,0x85,0x22] +# CHECK-ENCODING: [0x07,0x04,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 85 22 <unknown> +# CHECK-UNKNOWN: 07 04 85 02 <unknown> vl1re16.v v8, (a0) # CHECK-INST: vl1re16.v v8, (a0) -# CHECK-ENCODING: [0x07,0x54,0x85,0x22] +# CHECK-ENCODING: [0x07,0x54,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 85 22 <unknown> +# CHECK-UNKNOWN: 07 54 85 02 <unknown> vl1re32.v v8, (a0) # CHECK-INST: vl1re32.v v8, (a0) -# CHECK-ENCODING: [0x07,0x64,0x85,0x22] +# CHECK-ENCODING: [0x07,0x64,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 85 22 <unknown> +# CHECK-UNKNOWN: 07 64 85 02 <unknown> vl1re64.v v8, (a0) # CHECK-INST: vl1re64.v v8, (a0) -# CHECK-ENCODING: [0x07,0x74,0x85,0x22] +# CHECK-ENCODING: [0x07,0x74,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 74 85 22 <unknown> +# CHECK-UNKNOWN: 07 74 85 02 <unknown> vl2re8.v v8, (a0) # CHECK-INST: vl2re8.v v8, (a0) -# CHECK-ENCODING: [0x07,0x04,0x85,0x42] +# CHECK-ENCODING: [0x07,0x04,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 85 42 <unknown> +# CHECK-UNKNOWN: 07 04 85 22 <unknown> vl2re16.v v8, (a0) # CHECK-INST: vl2re16.v v8, (a0) -# CHECK-ENCODING: [0x07,0x54,0x85,0x42] +# CHECK-ENCODING: [0x07,0x54,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 85 42 <unknown> +# CHECK-UNKNOWN: 07 54 85 22 <unknown> vl2re32.v v8, (a0) # CHECK-INST: vl2re32.v v8, (a0) -# CHECK-ENCODING: [0x07,0x64,0x85,0x42] +# CHECK-ENCODING: [0x07,0x64,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 85 42 <unknown> +# CHECK-UNKNOWN: 07 64 85 22 <unknown> vl2re64.v v8, (a0) # CHECK-INST: vl2re64.v v8, (a0) -# CHECK-ENCODING: [0x07,0x74,0x85,0x42] +# CHECK-ENCODING: [0x07,0x74,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 74 85 42 <unknown> +# CHECK-UNKNOWN: 07 74 85 22 <unknown> vl4re8.v v8, (a0) # CHECK-INST: vl4re8.v v8, (a0) -# CHECK-ENCODING: [0x07,0x04,0x85,0x82] +# CHECK-ENCODING: [0x07,0x04,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 85 82 <unknown> +# CHECK-UNKNOWN: 07 04 85 62 <unknown> vl4re16.v v8, (a0) # CHECK-INST: vl4re16.v v8, (a0) -# CHECK-ENCODING: [0x07,0x54,0x85,0x82] +# CHECK-ENCODING: [0x07,0x54,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 85 82 <unknown> +# CHECK-UNKNOWN: 07 54 85 62 <unknown> vl4re32.v v8, (a0) # CHECK-INST: vl4re32.v v8, (a0) -# CHECK-ENCODING: [0x07,0x64,0x85,0x82] +# CHECK-ENCODING: [0x07,0x64,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 85 82 <unknown> +# CHECK-UNKNOWN: 07 64 85 62 <unknown> vl4re64.v v8, (a0) # CHECK-INST: vl4re64.v v8, (a0) -# CHECK-ENCODING: [0x07,0x74,0x85,0x82] +# CHECK-ENCODING: [0x07,0x74,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 74 85 82 <unknown> +# CHECK-UNKNOWN: 07 74 85 62 <unknown> vl8re8.v v8, (a0) # CHECK-INST: vl8re8.v v8, (a0) -# CHECK-ENCODING: [0x07,0x04,0x85,0x02] +# CHECK-ENCODING: [0x07,0x04,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 85 02 <unknown> +# CHECK-UNKNOWN: 07 04 85 e2 <unknown> vl8re16.v v8, (a0) # CHECK-INST: vl8re16.v v8, (a0) -# CHECK-ENCODING: [0x07,0x54,0x85,0x02] +# CHECK-ENCODING: [0x07,0x54,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 85 02 <unknown> +# CHECK-UNKNOWN: 07 54 85 e2 <unknown> vl8re32.v v8, (a0) # CHECK-INST: vl8re32.v v8, (a0) -# CHECK-ENCODING: [0x07,0x64,0x85,0x02] +# CHECK-ENCODING: [0x07,0x64,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 85 02 <unknown> +# CHECK-UNKNOWN: 07 64 85 e2 <unknown> vl8re64.v v8, (a0) # CHECK-INST: vl8re64.v v8, (a0) -# CHECK-ENCODING: [0x07,0x74,0x85,0x02] +# CHECK-ENCODING: [0x07,0x74,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 74 85 02 <unknown> +# CHECK-UNKNOWN: 07 74 85 e2 <unknown> diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s index e4795aa1c2c98..b5a75ac2d0087 100644 --- a/llvm/test/MC/RISCV/rvv/store.s +++ b/llvm/test/MC/RISCV/rvv/store.s @@ -208,24 +208,24 @@ vsoxei64.v v24, (a0), v4 vs1r.v v24, (a0) # CHECK-INST: vs1r.v v24, (a0) -# CHECK-ENCODING: [0x27,0x0c,0x85,0x22] +# CHECK-ENCODING: [0x27,0x0c,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 27 0c 85 22 <unknown> +# CHECK-UNKNOWN: 27 0c 85 02 <unknown> vs2r.v v24, (a0) # CHECK-INST: vs2r.v v24, (a0) -# CHECK-ENCODING: [0x27,0x0c,0x85,0x42] +# CHECK-ENCODING: [0x27,0x0c,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 27 0c 85 42 <unknown> +# CHECK-UNKNOWN: 27 0c 85 22 <unknown> vs4r.v v24, (a0) # CHECK-INST: vs4r.v v24, (a0) -# CHECK-ENCODING: [0x27,0x0c,0x85,0x82] +# CHECK-ENCODING: [0x27,0x0c,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 27 0c 85 82 <unknown> +# CHECK-UNKNOWN: 27 0c 85 62 <unknown> vs8r.v v24, (a0) # CHECK-INST: vs8r.v v24, (a0) -# CHECK-ENCODING: [0x27,0x0c,0x85,0x02] +# CHECK-ENCODING: [0x27,0x0c,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 27 0c 85 02 <unknown> +# CHECK-UNKNOWN: 27 0c 85 e2 <unknown> _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
