Author: Kazu Hirata Date: 2021-01-21T19:59:46-08:00 New Revision: c5c4dbd2790736008b1c60f1b737dfb824b90144
URL: https://github.com/llvm/llvm-project/commit/c5c4dbd2790736008b1c60f1b737dfb824b90144 DIFF: https://github.com/llvm/llvm-project/commit/c5c4dbd2790736008b1c60f1b737dfb824b90144.diff LOG: [CodeGen] Use llvm::append_range (NFC) Added: Modified: llvm/lib/CodeGen/Analysis.cpp llvm/lib/CodeGen/CodeGenPrepare.cpp llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp llvm/lib/CodeGen/MIRCanonicalizerPass.cpp llvm/lib/CodeGen/MachineCSE.cpp llvm/lib/CodeGen/MachineRegisterInfo.cpp llvm/lib/CodeGen/MachineVerifier.cpp llvm/lib/CodeGen/SplitKit.cpp Removed: ################################################################################ diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp index 67eb079afb49..ebeff1fec30b 100644 --- a/llvm/lib/CodeGen/Analysis.cpp +++ b/llvm/lib/CodeGen/Analysis.cpp @@ -733,8 +733,7 @@ static void collectEHScopeMembers( if (Visiting->isEHScopeReturnBlock()) continue; - for (const MachineBasicBlock *Succ : Visiting->successors()) - Worklist.push_back(Succ); + append_range(Worklist, Visiting->successors()); } } diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index c2fccab947d6..b2bc75c19709 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -3714,8 +3714,7 @@ class AddressingModeCombiner { PHINode::Create(CommonType, PredCount, "sunk_phi", CurrentPhi); Map[Current] = PHI; ST.insertNewPhi(PHI); - for (Value *P : CurrentPhi->incoming_values()) - Worklist.push_back(P); + append_range(Worklist, CurrentPhi->incoming_values()); } } } @@ -4969,8 +4968,7 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr, // For a PHI node, push all of its incoming values. if (PHINode *P = dyn_cast<PHINode>(V)) { - for (Value *IncValue : P->incoming_values()) - worklist.push_back(IncValue); + append_range(worklist, P->incoming_values()); PhiOrSelectSeen = true; continue; } diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 255ea693b5c4..e2a963747101 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -421,8 +421,7 @@ RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const { // Then the alternative mapping, if any. InstructionMappings AltMappings = getInstrAlternativeMappings(MI); - for (const InstructionMapping *AltMapping : AltMappings) - PossibleMappings.push_back(AltMapping); + append_range(PossibleMappings, AltMappings); #ifndef NDEBUG for (const InstructionMapping *Mapping : PossibleMappings) assert(Mapping->verify(MI) && "Mapping is invalid"); diff --git a/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp b/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp index b6fb6731d65c..8ef6aca602a1 100644 --- a/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp +++ b/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp @@ -85,9 +85,7 @@ static std::vector<MachineBasicBlock *> GetRPOList(MachineFunction &MF) { return {}; ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin()); std::vector<MachineBasicBlock *> RPOList; - for (auto MBB : RPOT) { - RPOList.push_back(MBB); - } + append_range(RPOList, RPOT); return RPOList; } diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index d8e95fa5cd6c..199fe2dc6454 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -748,8 +748,7 @@ bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) { Node = WorkList.pop_back_val(); Scopes.push_back(Node); OpenChildren[Node] = Node->getNumChildren(); - for (MachineDomTreeNode *Child : Node->children()) - WorkList.push_back(Child); + append_range(WorkList, Node->children()); } while (!WorkList.empty()); // Now perform CSE. @@ -861,8 +860,7 @@ bool MachineCSE::PerformSimplePRE(MachineDominatorTree *DT) { BBs.push_back(DT->getRootNode()); do { auto Node = BBs.pop_back_val(); - for (MachineDomTreeNode *Child : Node->children()) - BBs.push_back(Child); + append_range(BBs, Node->children()); MachineBasicBlock *MBB = Node->getBlock(); Changed |= ProcessBlockPRE(DT, MBB); diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index b34ea8162f72..5325eda9d478 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -631,8 +631,7 @@ void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) { if (IsUpdatedCSRsInitialized) UpdatedCSRs.clear(); - for (MCPhysReg Reg : CSRs) - UpdatedCSRs.push_back(Reg); + append_range(UpdatedCSRs, CSRs); // Zero value represents the end of the register list // (no more registers should be pushed). diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 9045019dc1ee..0f6d9b888f47 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -123,8 +123,7 @@ namespace { void addRegWithSubRegs(RegVector &RV, Register Reg) { RV.push_back(Reg); if (Reg.isPhysical()) - for (const MCPhysReg &SubReg : TRI->subregs(Reg.asMCReg())) - RV.push_back(SubReg); + append_range(RV, TRI->subregs(Reg.asMCReg())); } struct BBInfo { diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index 4be9847085b7..a6a3149ae25b 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -998,9 +998,7 @@ void SplitEditor::computeRedundantBackCopies( } if (!DominatedVNIs.empty()) { forceRecompute(0, *ParentVNI); - for (auto VNI : DominatedVNIs) { - BackCopies.push_back(VNI); - } + append_range(BackCopies, DominatedVNIs); DominatedVNIs.clear(); } } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
