Author: ShihPo Hung Date: 2021-01-19T19:09:56-08:00 New Revision: 4dae2247fd62f1319de6297fa5088ab1b0175d88
URL: https://github.com/llvm/llvm-project/commit/4dae2247fd62f1319de6297fa5088ab1b0175d88 DIFF: https://github.com/llvm/llvm-project/commit/4dae2247fd62f1319de6297fa5088ab1b0175d88.diff LOG: [RISCV] refactor VPatBinary (NFC) Make it easier to reuse for intrinsic vrgatherei16 which needs to encode both LMUL & EMUL in the instruction name, like PseudoVRGATHEREI16_VV_M1_M1 and PseudoVRGATHEREI16_VV_M1_M2. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D94951 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 85826b26eedf..4e08ab0d563c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1522,32 +1522,28 @@ class VPatUnaryAnyMask<string intrinsic, class VPatBinaryNoMask<string intrinsic_name, string inst, - string kind, ValueType result_type, ValueType op1_type, ValueType op2_type, int sew, - LMULInfo vlmul, VReg op1_reg_class, DAGOperand op2_kind> : Pat<(result_type (!cast<Intrinsic>(intrinsic_name) (op1_type op1_reg_class:$rs1), (op2_type op2_kind:$rs2), (XLenVT GPR:$vl))), - (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) + (!cast<Instruction>(inst) (op1_type op1_reg_class:$rs1), ToFPR32<op2_type, op2_kind, "rs2">.ret, (NoX0 GPR:$vl), sew)>; class VPatBinaryMask<string intrinsic_name, string inst, - string kind, ValueType result_type, ValueType op1_type, ValueType op2_type, ValueType mask_type, int sew, - LMULInfo vlmul, VReg result_reg_class, VReg op1_reg_class, DAGOperand op2_kind> : @@ -1557,7 +1553,7 @@ class VPatBinaryMask<string intrinsic_name, (op2_type op2_kind:$rs2), (mask_type V0), (XLenVT GPR:$vl))), - (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK") + (!cast<Instruction>(inst#"_MASK") (result_type result_reg_class:$merge), (op1_type op1_reg_class:$rs1), ToFPR32<op2_type, op2_kind, "rs2">.ret, @@ -1869,21 +1865,19 @@ multiclass VPatNullaryM<string intrinsic, string inst> { multiclass VPatBinary<string intrinsic, string inst, - string kind, ValueType result_type, ValueType op1_type, ValueType op2_type, ValueType mask_type, int sew, - LMULInfo vlmul, VReg result_reg_class, VReg op1_reg_class, DAGOperand op2_kind> { - def : VPatBinaryNoMask<intrinsic, inst, kind, result_type, op1_type, op2_type, - sew, vlmul, op1_reg_class, op2_kind>; - def : VPatBinaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type, - mask_type, sew, vlmul, result_reg_class, op1_reg_class, + def : VPatBinaryNoMask<intrinsic, inst, result_type, op1_type, op2_type, + sew, op1_reg_class, op2_kind>; + def : VPatBinaryMask<intrinsic, inst, result_type, op1_type, op2_type, + mask_type, sew, result_reg_class, op1_reg_class, op2_kind>; } @@ -1951,9 +1945,9 @@ multiclass VPatConversion<string intrinsic, multiclass VPatBinaryV_VV<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in - defm : VPatBinary<intrinsic, instruction, "VV", - vti.Vector, vti.Vector, vti.Vector, vti.Mask, - vti.SEW, vti.LMul, vti.RegClass, + defm : VPatBinary<intrinsic, instruction # "_VV_" # vti.LMul.MX, + vti.Vector, vti.Vector, vti.Vector,vti.Mask, + vti.SEW, vti.RegClass, vti.RegClass, vti.RegClass>; } @@ -1961,46 +1955,47 @@ multiclass VPatBinaryV_VV_INT<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in { defvar ivti = GetIntVTypeInfo<vti>.Vti; - defm : VPatBinary<intrinsic, instruction, "VV", + defm : VPatBinary<intrinsic, instruction # "_VV_" # vti.LMul.MX, vti.Vector, vti.Vector, ivti.Vector, vti.Mask, - vti.SEW, vti.LMul, vti.RegClass, + vti.SEW, vti.RegClass, vti.RegClass, vti.RegClass>; } } multiclass VPatBinaryV_VX<string intrinsic, string instruction, list<VTypeInfo> vtilist> { - foreach vti = vtilist in - defm : VPatBinary<intrinsic, instruction, - !if(!eq(vti.Scalar, XLenVT), "VX", "VF"), + foreach vti = vtilist in { + defvar kind = !if(!eq(vti.Scalar, XLenVT), "_VX_", "_VF_"); + defm : VPatBinary<intrinsic, instruction # kind # vti.LMul.MX, vti.Vector, vti.Vector, vti.Scalar, vti.Mask, - vti.SEW, vti.LMul, vti.RegClass, + vti.SEW, vti.RegClass, vti.RegClass, vti.ScalarRegClass>; + } } multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in - defm : VPatBinary<intrinsic, instruction, "VX", + defm : VPatBinary<intrinsic, instruction # "_VX_" # vti.LMul.MX, vti.Vector, vti.Vector, XLenVT, vti.Mask, - vti.SEW, vti.LMul, vti.RegClass, + vti.SEW, vti.RegClass, vti.RegClass, GPR>; } multiclass VPatBinaryV_VI<string intrinsic, string instruction, list<VTypeInfo> vtilist, Operand imm_type> { foreach vti = vtilist in - defm : VPatBinary<intrinsic, instruction, "VI", + defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX, vti.Vector, vti.Vector, XLenVT, vti.Mask, - vti.SEW, vti.LMul, vti.RegClass, + vti.SEW, vti.RegClass, vti.RegClass, imm_type>; } multiclass VPatBinaryM_MM<string intrinsic, string instruction> { foreach mti = AllMasks in - def : VPatBinaryNoMask<intrinsic, instruction, "MM", + def : VPatBinaryNoMask<intrinsic, instruction # "_MM_" # mti.LMul.MX, mti.Mask, mti.Mask, mti.Mask, - mti.SEW, mti.LMul, VR, VR>; + mti.SEW, VR, VR>; } multiclass VPatBinaryW_VV<string intrinsic, string instruction, @@ -2008,9 +2003,9 @@ multiclass VPatBinaryW_VV<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defm : VPatBinary<intrinsic, instruction, "VV", + defm : VPatBinary<intrinsic, instruction # "_VV_" # Vti.LMul.MX, Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask, - Vti.SEW, Vti.LMul, Wti.RegClass, + Vti.SEW, Wti.RegClass, Vti.RegClass, Vti.RegClass>; } } @@ -2020,10 +2015,10 @@ multiclass VPatBinaryW_VX<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defm : VPatBinary<intrinsic, instruction, - !if(!eq(Vti.Scalar, XLenVT), "VX", "VF"), + defvar kind = !if(!eq(Vti.Scalar, XLenVT), "_VX_", "_VF_"); + defm : VPatBinary<intrinsic, instruction # kind # Vti.LMul.MX, Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask, - Vti.SEW, Vti.LMul, Wti.RegClass, + Vti.SEW, Wti.RegClass, Vti.RegClass, Vti.ScalarRegClass>; } } @@ -2033,9 +2028,9 @@ multiclass VPatBinaryW_WV<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defm : VPatBinary<intrinsic, instruction, "WV", + defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX, Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, - Vti.SEW, Vti.LMul, Wti.RegClass, + Vti.SEW, Wti.RegClass, Wti.RegClass, Vti.RegClass>; } } @@ -2045,10 +2040,10 @@ multiclass VPatBinaryW_WX<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defm : VPatBinary<intrinsic, instruction, - !if(!eq(Vti.Scalar, XLenVT), "WX", "WF"), + defvar kind = !if(!eq(Vti.Scalar, XLenVT), "_WX_", "_WF_"); + defm : VPatBinary<intrinsic, instruction # kind # Vti.LMul.MX, Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, - Vti.SEW, Vti.LMul, Wti.RegClass, + Vti.SEW, Wti.RegClass, Wti.RegClass, Vti.ScalarRegClass>; } } @@ -2058,9 +2053,9 @@ multiclass VPatBinaryV_WV<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defm : VPatBinary<intrinsic, instruction, "WV", + defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX, Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, - Vti.SEW, Vti.LMul, Vti.RegClass, + Vti.SEW, Vti.RegClass, Wti.RegClass, Vti.RegClass>; } } @@ -2070,10 +2065,10 @@ multiclass VPatBinaryV_WX<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defm : VPatBinary<intrinsic, instruction, - !if(!eq(Vti.Scalar, XLenVT), "WX", "WF"), + defvar kind = !if(!eq(Vti.Scalar, XLenVT), "_WX_", "_WF_"); + defm : VPatBinary<intrinsic, instruction # kind # Vti.LMul.MX, Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, - Vti.SEW, Vti.LMul, Vti.RegClass, + Vti.SEW, Vti.RegClass, Wti.RegClass, Vti.ScalarRegClass>; } } @@ -2083,9 +2078,9 @@ multiclass VPatBinaryV_WI<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defm : VPatBinary<intrinsic, instruction, "WI", + defm : VPatBinary<intrinsic, instruction # "_WI_" # Vti.LMul.MX, Vti.Vector, Wti.Vector, XLenVT, Vti.Mask, - Vti.SEW, Vti.LMul, Vti.RegClass, + Vti.SEW, Vti.RegClass, Wti.RegClass, uimm5>; } } @@ -2150,28 +2145,29 @@ multiclass VPatBinaryV_I<string intrinsic, string instruction> { multiclass VPatBinaryM_VV<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in - defm : VPatBinary<intrinsic, instruction, "VV", + defm : VPatBinary<intrinsic, instruction # "_VV_" # vti.LMul.MX, vti.Mask, vti.Vector, vti.Vector, vti.Mask, - vti.SEW, vti.LMul, VR, + vti.SEW, VR, vti.RegClass, vti.RegClass>; } multiclass VPatBinaryM_VX<string intrinsic, string instruction, list<VTypeInfo> vtilist> { - foreach vti = vtilist in - defm : VPatBinary<intrinsic, instruction, - !if(!eq(vti.Scalar, XLenVT), "VX", "VF"), + foreach vti = vtilist in { + defvar kind = !if(!eq(vti.Scalar, XLenVT), "_VX_", "_VF_"); + defm : VPatBinary<intrinsic, instruction # kind # vti.LMul.MX, vti.Mask, vti.Vector, vti.Scalar, vti.Mask, - vti.SEW, vti.LMul, VR, + vti.SEW, VR, vti.RegClass, vti.ScalarRegClass>; + } } multiclass VPatBinaryM_VI<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in - defm : VPatBinary<intrinsic, instruction, "VI", + defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX, vti.Mask, vti.Vector, XLenVT, vti.Mask, - vti.SEW, vti.LMul, VR, + vti.SEW, VR, vti.RegClass, simm5>; } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
