Author: Hsiangkai Wang Date: 2021-01-16T23:21:29+08:00 New Revision: 098dbf190a5586d02f48b84eb41b93b701cdeb97
URL: https://github.com/llvm/llvm-project/commit/098dbf190a5586d02f48b84eb41b93b701cdeb97 DIFF: https://github.com/llvm/llvm-project/commit/098dbf190a5586d02f48b84eb41b93b701cdeb97.diff LOG: [RISCV] Correct alignment settings for vector registers. According to "9. Vector Memory Alignment Constraints" in V specification, the alignment of vector memory access is aligned to the size of the element. In our current implementation, we support ELEN up to 64. We could assume the alignment of vector registers is 64 under the assumption. Differential Revision: https://reviews.llvm.org/D94751 Added: Modified: llvm/lib/Target/RISCV/RISCVRegisterInfo.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 99f74bfc2a09..75615fd334b7 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -386,11 +386,10 @@ let RegAltNameIndices = [ABIRegAltName] in { class VReg<list<ValueType> regTypes, dag regList, int Vlmul> : RegisterClass<"RISCV", regTypes, - // FIXME: Spill alignment set to 16 bytes. - 128, + 64, // The maximum supported ELEN is 64. regList> { int VLMul = Vlmul; - int Size = !mul(Vlmul, 64); // FIXME: assuming ELEN=64 + int Size = !mul(Vlmul, 64); } def VR : VReg<[vint8mf2_t, vint8mf4_t, vint8mf8_t, _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
